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LF-Building-a-RISC-V-CPU-Core
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  • ff0ec641d2
         Add data memory and implement store/load main Victor Timofei 2022-01-16 21:48:31 +0200
  • d2b945d974
         Add Jump instructions Victor Timofei 2022-01-16 20:36:50 +0200
  • ce288f2840
         Merge branch 'stevehoover:main' into main Victor Timofei 2022-01-16 19:20:20 +0200
  • c98b2fc672
         Complete ALU Victor Timofei 2022-01-16 14:22:57 +0200
  • 26bc694325
         Fix decoder Victor Timofei 2022-01-16 14:22:40 +0200
  • 97e7881dbe
         Decode the rest instructions Victor Timofei 2022-01-16 12:53:15 +0200
  • dcd5e407e3 \viz_alpha -> \viz_js Added $ to missing signals VIZ. Steve Hoover 2022-01-14 15:15:19 -0500
  • dac60392eb \viz_alpha -> \viz_js Steve Hoover 2022-01-14 13:25:47 -0500
  • 8fc1626ae3
         Change test Victor Timofei 2022-01-11 21:58:01 +0200
  • 7085ac35bc
         Replace passed check Victor Timofei 2022-01-11 21:50:47 +0200
  • 0f3b747dc7
         Cleanup bogus use Victor Timofei 2022-01-11 21:46:04 +0200
  • 6c08931ddd
         Implement branch Victor Timofei 2022-01-11 21:44:11 +0200
  • a7d3c26f76
         Disable writing to register 0 Victor Timofei 2022-01-11 21:20:03 +0200
  • 92c9d9c91e
         Connect result to write data Victor Timofei 2022-01-11 21:18:10 +0200
  • 85eebd8a1b
         Add `add` instructions for ALU and disable write Victor Timofei 2022-01-11 21:04:31 +0200
  • 432ce28d5d
         Add register file Victor Timofei 2022-01-11 20:44:57 +0200
  • f6b0d66747
         Decode instructions Victor Timofei 2022-01-10 23:50:30 +0200
  • be9fe44a80
         Extract instruction fields Victor Timofei 2022-01-10 23:28:03 +0200
  • 959a2f5eec
         Merge branch 'stevehoover:main' into main Victor Timofei 2022-01-10 22:07:31 +0200
  • 77577c5d03
         Fix binary literal Victor Timofei 2022-01-10 22:06:15 +0200
  • 6c05fd21ef
         Decode instruction types Victor Timofei 2022-01-10 22:04:05 +0200
  • d5bb6da13c
         Add instruction memory Victor Timofei 2022-01-10 21:19:32 +0200
  • b3412a9706
         Add program counter Victor Timofei 2022-01-10 21:01:15 +0200
  • 977e7124bb Fix. Steve Hoover 2021-12-15 18:41:02 -0500
  • a0a5d1f72c Ignore .bak files. Steve Hoover 2021-12-15 18:34:50 -0500
  • 9468717352 Updates for newer Fabric/VIZ. Steve Hoover 2021-12-15 18:04:04 -0500
  • 0e71e94d9c Removed bug workaround. Steve Hoover 2021-08-26 11:44:43 -0400
  • 9dea12acf9
         Delete full_riscv.tlv Steve Hoover 2021-07-28 18:09:27 -0400
  • 0dae4321ff
         Update risc-v_solutions.tlv Steve Hoover 2021-03-28 19:59:52 -0400
  • 378872dede Added banner, course link, and next steps links. Steve Hoover 2021-03-01 16:29:27 -0500
  • dbf18f4d36 Updated SVG. Steve Hoover 2021-03-01 15:50:23 -0500
  • cd462a8a8d Updated m4+dmem(..) to have a single address argument. Steve Hoover 2021-02-28 17:55:15 -0500
  • c2b5ff0171 Providing bit widths on array macro inputs. Steve Hoover 2021-02-27 19:05:01 -0500
  • b24f7ea69f Enabled bit-width checking. Steve Hoover 2021-02-27 17:03:26 -0500
  • a1b664f8a6 minor. Steve Hoover 2021-02-27 15:49:57 -0500
  • d2e0c8cbcf minor. Steve Hoover 2021-02-27 15:38:14 -0500
  • 4ed61feeeb Made values hexadecimal in VIZ for full test program. Steve Hoover 2021-02-26 20:17:40 -0500
  • 3de301a7ed Test prog macro again needs to define cycle count. Steve Hoover 2021-02-26 20:04:24 -0500
  • 4efdd7838c Restored \TLV test_prog() for reference solutions. Steve Hoover 2021-02-26 19:56:16 -0500
  • 67042549b7 Reworking the way test_prog works. Steve Hoover 2021-02-26 19:42:23 -0500
  • 93d3108a30 Include //m4+test_prog in shell because it must be instantiated in the right place. Steve Hoover 2021-02-26 18:33:23 -0500
  • 09f187f917 Allow m4+test_prog after use of M4_MAX_CYC. Steve Hoover 2021-02-26 18:27:40 -0500
  • f86204080c Resolving issue with m4_asm_end which must be used from both \TLV and \SV context. Use of new signal goTo* functions in VIZ. Readme updates. Steve Hoover 2021-02-26 17:43:18 -0500
  • 315e5d541a Updated shell code to use x vs. r for regs. Steve Hoover 2021-02-17 20:21:21 -0500
  • c3472c5480 Updated from r -> x in decode VIZ. Steve Hoover 2021-02-17 20:14:19 -0500
  • 876efb8faa Updated regs to x vs r. Steve Hoover 2021-02-17 19:57:32 -0500
  • 62288d1b08 Merge branch 'main' of github.com:stevehoover/LF-Building-a-RISC-V-CPU-Core into main Steve Hoover 2021-02-17 19:49:26 -0500
  • e5981f0b05 Update WARP-V to allow xX vs. rX register names. Steve Hoover 2021-02-17 19:49:15 -0500
  • 87d119179d
         Update README.md Steve Hoover 2021-02-17 17:40:39 -0500
  • 42316d6e24
         Update README.md Steve Hoover 2021-02-17 17:38:52 -0500
  • ac8c3f8e94
         Update README.md Steve Hoover 2021-02-17 17:36:29 -0500
  • aa0e1a756b Prepping shell and reference solutions. Steve Hoover 2021-02-17 17:33:13 -0500
  • 74d2ba2733 Tweaks. Steve Hoover 2021-02-16 22:26:22 -0500
  • d0860624b7 Quick fixes. Steve Hoover 2021-02-15 21:55:36 -0500
  • b8f6da26d0 Misc updates. Steve Hoover 2021-02-15 21:49:35 -0500
  • b46acf235f WIP improvements to RISC-V VIZ, etc. Steve Hoover 2021-02-11 21:18:16 -0500
  • f9047e6dc0 fix Steve Hoover 2021-02-09 19:13:38 -0500
  • d3872a0fe1 Refinements to full_riscv.tlv and copied to lib/risc-v_shell_lib.tlv to serve as reference solution and library. Steve Hoover 2021-02-09 18:22:48 -0500
  • dfa3bfe8be
         Update risc-v_shell.tlv Shivam Potdar 2021-02-09 19:26:03 +0530
  • cd42316a04
         Update risc-v_shell.tlv Steve Hoover 2021-02-08 14:45:26 -0500
  • d4492c268b
         Update README.md Steve Hoover 2021-02-08 14:37:13 -0500
  • 67ea239ec0
         Update risc-v_shell.tlv Steve Hoover 2021-02-08 13:53:03 -0500
  • a25f70e45b
         Update README.md Steve Hoover 2021-02-08 13:51:19 -0500
  • 5165d3a3b8
         Update README.md Steve Hoover 2021-02-08 13:50:44 -0500
  • f206e7a370 initial - riscv files Shivam Potdar 2021-02-08 21:10:43 +0530
  • 18173c0402 Added lib/calc_viz.tlv. Steve Hoover 2021-02-04 18:40:58 -0500
  • ccd165ac54
         Create README.md Steve Hoover 2021-01-29 11:32:06 -0500