Tweaks.
This commit is contained in:
Steve Hoover
parent
d0860624b7
commit
74d2ba2733
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@ -234,7 +234,7 @@ m4+definitions(['
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})
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let passed = new fabric.Text("", {
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top: 300,
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top: 340,
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left: -30,
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fontSize: 46,
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fontWeight: 800
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@ -336,7 +336,6 @@ m4+definitions(['
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let rs2_valid = siggen("rs2_valid")
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let ld_data = siggen("ld_data")
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let mnemonic = siggen_mnemonic()
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let dummy = siggen("dummy")
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let passed = siggen("passed_cond", false, false)
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let rf_rd_en1 = siggen_rf_dmem("rf1_rd_en1")
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@ -573,7 +572,7 @@ m4+definitions(['
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} else {
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// Using an unstable API, so:
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try {
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passed.goTo(passed.sikkkgnal.waveData.endCycle - 1)
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passed.goTo(passed.signal.waveData.endCycle - 1)
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if (passed.asBool()) {
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this.getInitObject("passed").set({text:"Sim Passes", visible: true, fill: "lightgray"})
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}
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@ -622,12 +621,12 @@ m4+definitions(['
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let instr = this.svSigRef(`instrs(${this.getIndex()})`)
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if (instr) {
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let binary_str = instr.asBinaryStr("")
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let binary_str = instr.goTo(0).asBinaryStr("")
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this.getInitObject("binary").setText(binary_str)
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}
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let disassembled = this.svSigRef(`instr_strs(${this.getIndex()})`)
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if (disassembled) {
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let disassembled_str = disassembled.asString("")
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let disassembled_str = disassembled.goTo(0).asString("")
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disassembled_str = disassembled_str.slice(0, -5)
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this.getInitObject("disassembled").setText(disassembled_str)
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}
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@ -649,65 +648,90 @@ m4+definitions(['
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// Some constant values to use as operands.
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m4_asm(ADDI, r1, r0, 10101) // An operand value of 21.
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m4_asm(ADDI, r2, r0, 111) // An operand value of 7.
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m4_asm(XORI, r3, r0, 111111111100) // An operand value of -4.
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m4_asm(ADDI, r3, r0, 111111111100) // An operand value of -4.
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// Execute one of each instruction, XORing subtracting (via ADDI) the expected value.
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// ANDI:
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m4_asm(ANDI, r5, r1, 1011100)
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m4_asm(XORI, r5, r5, 10100)
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m4_asm(XORI, r5, r5, 10101)
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// ORI:
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m4_asm(ORI, r6, r1, 1011100)
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m4_asm(XORI, r6, r6, 1011101)
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m4_asm(XORI, r6, r6, 1011100)
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// ADDI:
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m4_asm(ADDI, r7, r1, 111)
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m4_asm(XORI, r7, r7, 11100)
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m4_asm(XORI, r7, r7, 11101)
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// ADDI:
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m4_asm(SLLI, r8, r1, 110)
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m4_asm(XORI, r8, r8, 10101000000)
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m4_asm(XORI, r8, r8, 10101000001)
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// SLLI:
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m4_asm(SRLI, r9, r1, 10)
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m4_asm(XORI, r9, r9, 101)
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m4_asm(XORI, r9, r9, 100)
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// AND:
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m4_asm(AND, r10, r1, r2)
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m4_asm(XORI, r10, r10, 101)
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m4_asm(XORI, r10, r10, 100)
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// OR:
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m4_asm(OR, r11, r1, r2)
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m4_asm(XORI, r11, r11, 10111)
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m4_asm(XORI, r11, r11, 10110)
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// XOR:
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m4_asm(XOR, r12, r1, r2)
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m4_asm(XORI, r12, r12, 10010)
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m4_asm(XORI, r12, r12, 10011)
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// ADD:
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m4_asm(ADD, r13, r1, r2)
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m4_asm(XORI, r13, r13, 11100)
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m4_asm(XORI, r13, r13, 11101)
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// SUB:
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m4_asm(SUB, r14, r1, r2)
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m4_asm(XORI, r14, r14, 1110)
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m4_asm(XORI, r14, r14, 1111)
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// SLL:
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m4_asm(SLL, r15, r2, r2)
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m4_asm(XORI, r15, r15, 1110000000)
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m4_asm(XORI, r15, r15, 1110000001)
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// SRL:
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m4_asm(SRL, r16, r1, r2)
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m4_asm(XORI, r16, r16, 0)
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m4_asm(XORI, r16, r16, 1)
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// SLTU:
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m4_asm(SLTU, r17, r2, r1)
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m4_asm(XORI, r17, r17, 1)
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m4_asm(XORI, r17, r17, 0)
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// SLTIU:
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m4_asm(SLTIU, r18, r2, 10101)
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m4_asm(XORI, r18, r18, 1)
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m4_asm(XORI, r18, r18, 0)
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// LUI:
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m4_asm(LUI, r19, 0)
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m4_asm(XORI, r19, r19, 0)
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m4_asm(XORI, r19, r19, 1)
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// SRAI:
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m4_asm(SRAI, r20, r3, 1)
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m4_asm(XORI, r20, r20, 111111111110)
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m4_asm(XORI, r20, r20, 111111111111)
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// SLT:
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m4_asm(SLT, r21, r3, r1)
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m4_asm(XORI, r21, r21, 1)
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m4_asm(XORI, r21, r21, 0)
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// SLTI:
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m4_asm(SLTI, r22, r3, 1)
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m4_asm(XORI, r22, r22, 1)
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m4_asm(XORI, r22, r22, 0)
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// SRA:
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m4_asm(SRA, r23, r1, r2)
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m4_asm(XORI, r23, r23, 0)
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// Test AUIPC. PC is >= 32 and < 64 instructions. JAL, and JALR together. Their PCs should differ by 4.
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m4_asm(XORI, r23, r23, 1)
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// AUIPC:
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m4_asm(AUIPC, r4, 100)
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m4_asm(SRLI, r24, r4, 111)
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m4_asm(XORI, r24, r24, 10000001)
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m4_asm(XORI, r24, r24, 10000000)
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// JAL:
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m4_asm(JAL, r25, 10) // r25 = PC of next instr
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m4_asm(AUIPC, r4, 0) // r4 = PC
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m4_asm(XOR, r25, r25, r4) # AUIPC and JAR results are the same.
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m4_asm(JALR, r26, r4, 1100)
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m4_asm(SUB, r26, r26, r4) // JALR PC+4 - AUIPC PC
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m4_asm(XORI, r26, r26, 1100) // - 4 instrs
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//m4_asm(SW, r27,
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m4_asm(AUIPC, r4, 0) // r4 = PC
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m4_asm(XOR, r25, r25, r4) # AUIPC and JAR results are the same.
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m4_asm(XORI, r25, r25, 1)
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// JALR:
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m4_asm(JALR, r26, r4, 10000)
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m4_asm(SUB, r26, r26, r4) // JALR PC+4 - AUIPC PC
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m4_asm(ADDI, r26, r26, 111111110001) // - 4 instrs, + 1
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// SW & LW:
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m4_asm(SW, r2, r1, 1)
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m4_asm(LW, r27, r2, 1)
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m4_asm(XOR, r27, r27, r1)
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// Set r30[0], so always report passed on completion, regardless of registers containing zeros.
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m4_asm(XORI, r27, r27, 10100)
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// Write 1 to remaining registers prior to r30 just to avoid concern.
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m4_asm(ADDI, r28, r0, 1)
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m4_asm(ADDI, r29, r0, 1)
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// Terminate with success condition (regardless of correctness of register values):
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m4_asm(ADDI, r30, r0, 1)
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m4_asm(JAL, r0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
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m4_asm_end()
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m4_define(['M4_MAX_CYC'], 50)
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m4_define(['M4_MAX_CYC'], 70)
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\TLV sum_prog()
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// /====================\
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@ -733,7 +757,7 @@ m4+definitions(['
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m4_asm(ADDI, r30, r14, 111111010100) // Subtract expected value of 44 to set r30 to 1 if and only iff the result is 45 (1 + 2 + ... + 9).
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m4_asm(BGE, r0, r0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
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m4_asm_end()
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m4_define(['M4_MAX_CYC'], 50)
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m4_define(['M4_MAX_CYC'], 40)
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// ^===================================================================^
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@ -745,7 +769,7 @@ m4+definitions(['
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// Possible choices for M4_LAB.
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// START, PC, IMEM, INSTR_TYPE, FIELDS, IMM, SUBSET_INSTRS, RF_MACRO, RF_READ, SUBSET_ALU, RF_WRITE, TAKEN_BR, BR_REDIR, TB,
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// TEST_PROG, ALL_INSTRS, FULL_ALU, JUMP, LD_ST_ADDR, DMEM, LD_DATA, DONE
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m4_default(['M4_LAB'], M4_START_LAB)
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m4_default(['M4_LAB'], M4_DONE_LAB)
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// @@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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/* Built for LAB: M4_LAB */
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