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LF-Building-a-RISC-V-CPU-Core
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Update risc-v_shell.tlv

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Steve Hoover 2021-02-08 14:45:26 -05:00 committed by GitHub
parent d4492c268b
commit cd42316a04
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risc-v_shell.tlv
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@ -2,7 +2,7 @@
\SV
// This code can be found in: https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/risc-v_shell.tlv
m4_include_lib(['https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/lib/risc-v_shell_lib.tlv'])
m4_include_lib(['https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/main/lib/risc-v_shell_lib.tlv'])
\SV
m4_makerchip_module // (Expanded in Nav-TLV pane.)