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LF-Building-a-RISC-V-CPU-Core
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Fix.

This commit is contained in:
Steve Hoover 2021-12-15 18:41:02 -05:00
parent a0a5d1f72c
commit 977e7124bb
1 changed files with 1 additions and 1 deletions
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2
lib/risc-v_shell_lib.tlv
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@ -710,7 +710,7 @@ m4+definitions(['
let instr = this.svSigRef(`instrs(${this.getIndex()})`)
if (instr) {
let binary_str = instr.goToSimStart().asBinaryStr("")
this.getInitObject("binary").set(text: binary_str})
this.getInitObject("binary").set({text: binary_str})
}
let disassembled = this.svSigRef(`instr_strs(${this.getIndex()})`)
if (disassembled) {