Steve Hoover
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dbf18f4d36
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Updated SVG.
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2021-03-01 15:50:23 -05:00 |
Steve Hoover
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cd462a8a8d
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Updated m4+dmem(..) to have a single address argument.
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2021-02-28 17:55:15 -05:00 |
Steve Hoover
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c2b5ff0171
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Providing bit widths on array macro inputs.
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2021-02-27 19:05:01 -05:00 |
Steve Hoover
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b24f7ea69f
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Enabled bit-width checking.
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2021-02-27 17:03:26 -05:00 |
Steve Hoover
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a1b664f8a6
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minor.
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2021-02-27 15:49:57 -05:00 |
Steve Hoover
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d2e0c8cbcf
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minor.
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2021-02-27 15:38:14 -05:00 |
Steve Hoover
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4ed61feeeb
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Made values hexadecimal in VIZ for full test program.
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2021-02-26 20:17:40 -05:00 |
Steve Hoover
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3de301a7ed
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Test prog macro again needs to define cycle count.
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2021-02-26 20:04:24 -05:00 |
Steve Hoover
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4efdd7838c
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Restored \TLV test_prog() for reference solutions.
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2021-02-26 19:56:16 -05:00 |
Steve Hoover
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67042549b7
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Reworking the way test_prog works.
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2021-02-26 19:42:23 -05:00 |
Steve Hoover
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93d3108a30
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Include //m4+test_prog in shell because it must be instantiated in the right place.
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2021-02-26 18:33:23 -05:00 |
Steve Hoover
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09f187f917
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Allow m4+test_prog after use of M4_MAX_CYC.
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2021-02-26 18:27:40 -05:00 |
Steve Hoover
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f86204080c
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Resolving issue with m4_asm_end which must be used from both \TLV and \SV context.
Use of new signal goTo* functions in VIZ.
Readme updates.
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2021-02-26 17:43:18 -05:00 |
Steve Hoover
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315e5d541a
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Updated shell code to use x vs. r for regs.
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2021-02-17 20:21:21 -05:00 |
Steve Hoover
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c3472c5480
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Updated from r -> x in decode VIZ.
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2021-02-17 20:14:19 -05:00 |
Steve Hoover
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876efb8faa
|
Updated regs to x vs r.
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2021-02-17 19:57:32 -05:00 |
Steve Hoover
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62288d1b08
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Merge branch 'main' of github.com:stevehoover/LF-Building-a-RISC-V-CPU-Core into main
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2021-02-17 19:49:26 -05:00 |
Steve Hoover
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e5981f0b05
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Update WARP-V to allow xX vs. rX register names.
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2021-02-17 19:49:15 -05:00 |
Steve Hoover
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87d119179d
|
Update README.md
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2021-02-17 17:40:39 -05:00 |
Steve Hoover
|
42316d6e24
|
Update README.md
|
2021-02-17 17:38:52 -05:00 |
Steve Hoover
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ac8c3f8e94
|
Update README.md
Updated reference solutions link.
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2021-02-17 17:36:29 -05:00 |
Steve Hoover
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aa0e1a756b
|
Prepping shell and reference solutions.
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2021-02-17 17:33:13 -05:00 |
Steve Hoover
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74d2ba2733
|
Tweaks.
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2021-02-16 22:26:22 -05:00 |
Steve Hoover
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d0860624b7
|
Quick fixes.
|
2021-02-15 21:55:36 -05:00 |
Steve Hoover
|
b8f6da26d0
|
Misc updates.
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2021-02-15 21:49:35 -05:00 |
Steve Hoover
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b46acf235f
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WIP improvements to RISC-V VIZ, etc.
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2021-02-11 21:18:16 -05:00 |
Steve Hoover
|
f9047e6dc0
|
fix
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2021-02-09 19:13:38 -05:00 |
Steve Hoover
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d3872a0fe1
|
Refinements to full_riscv.tlv and copied to lib/risc-v_shell_lib.tlv to serve as reference solution and library.
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2021-02-09 18:22:48 -05:00 |
Shivam Potdar
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dfa3bfe8be
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Update risc-v_shell.tlv
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2021-02-09 19:26:03 +05:30 |
Steve Hoover
|
cd42316a04
|
Update risc-v_shell.tlv
|
2021-02-08 14:45:26 -05:00 |
Steve Hoover
|
d4492c268b
|
Update README.md
|
2021-02-08 14:37:13 -05:00 |
Steve Hoover
|
67ea239ec0
|
Update risc-v_shell.tlv
|
2021-02-08 13:53:03 -05:00 |
Steve Hoover
|
a25f70e45b
|
Update README.md
|
2021-02-08 13:51:19 -05:00 |
Steve Hoover
|
5165d3a3b8
|
Update README.md
|
2021-02-08 13:50:44 -05:00 |
Shivam Potdar
|
f206e7a370
|
initial - riscv files
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2021-02-08 21:10:43 +05:30 |
Steve Hoover
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18173c0402
|
Added lib/calc_viz.tlv.
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2021-02-04 18:40:58 -05:00 |
Steve Hoover
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ccd165ac54
|
Create README.md
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2021-01-29 11:32:06 -05:00 |