Commit Graph

21 Commits

Author SHA1 Message Date
Steve Hoover 62288d1b08 Merge branch 'main' of github.com:stevehoover/LF-Building-a-RISC-V-CPU-Core into main 2021-02-17 19:49:26 -05:00
Steve Hoover e5981f0b05 Update WARP-V to allow xX vs. rX register names. 2021-02-17 19:49:15 -05:00
Steve Hoover 87d119179d
Update README.md 2021-02-17 17:40:39 -05:00
Steve Hoover 42316d6e24
Update README.md 2021-02-17 17:38:52 -05:00
Steve Hoover ac8c3f8e94
Update README.md
Updated reference solutions link.
2021-02-17 17:36:29 -05:00
Steve Hoover aa0e1a756b Prepping shell and reference solutions. 2021-02-17 17:33:13 -05:00
Steve Hoover 74d2ba2733 Tweaks. 2021-02-16 22:26:22 -05:00
Steve Hoover d0860624b7 Quick fixes. 2021-02-15 21:55:36 -05:00
Steve Hoover b8f6da26d0 Misc updates. 2021-02-15 21:49:35 -05:00
Steve Hoover b46acf235f WIP improvements to RISC-V VIZ, etc. 2021-02-11 21:18:16 -05:00
Steve Hoover f9047e6dc0 fix 2021-02-09 19:13:38 -05:00
Steve Hoover d3872a0fe1 Refinements to full_riscv.tlv and copied to lib/risc-v_shell_lib.tlv to serve as reference solution and library. 2021-02-09 18:22:48 -05:00
Shivam Potdar dfa3bfe8be
Update risc-v_shell.tlv 2021-02-09 19:26:03 +05:30
Steve Hoover cd42316a04
Update risc-v_shell.tlv 2021-02-08 14:45:26 -05:00
Steve Hoover d4492c268b
Update README.md 2021-02-08 14:37:13 -05:00
Steve Hoover 67ea239ec0
Update risc-v_shell.tlv 2021-02-08 13:53:03 -05:00
Steve Hoover a25f70e45b
Update README.md 2021-02-08 13:51:19 -05:00
Steve Hoover 5165d3a3b8
Update README.md 2021-02-08 13:50:44 -05:00
Shivam Potdar f206e7a370 initial - riscv files 2021-02-08 21:10:43 +05:30
Steve Hoover 18173c0402 Added lib/calc_viz.tlv. 2021-02-04 18:40:58 -05:00
Steve Hoover ccd165ac54
Create README.md 2021-01-29 11:32:06 -05:00