Steve Hoover
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315e5d541a
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Updated shell code to use x vs. r for regs.
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2021-02-17 20:21:21 -05:00 |
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Steve Hoover
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c3472c5480
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Updated from r -> x in decode VIZ.
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2021-02-17 20:14:19 -05:00 |
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Steve Hoover
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876efb8faa
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Updated regs to x vs r.
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2021-02-17 19:57:32 -05:00 |
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Steve Hoover
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62288d1b08
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Merge branch 'main' of github.com:stevehoover/LF-Building-a-RISC-V-CPU-Core into main
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2021-02-17 19:49:26 -05:00 |
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Steve Hoover
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e5981f0b05
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Update WARP-V to allow xX vs. rX register names.
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2021-02-17 19:49:15 -05:00 |
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Steve Hoover
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87d119179d
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Update README.md
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2021-02-17 17:40:39 -05:00 |
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Steve Hoover
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42316d6e24
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Update README.md
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2021-02-17 17:38:52 -05:00 |
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Steve Hoover
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ac8c3f8e94
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Update README.md
Updated reference solutions link.
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2021-02-17 17:36:29 -05:00 |
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Steve Hoover
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aa0e1a756b
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Prepping shell and reference solutions.
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2021-02-17 17:33:13 -05:00 |
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Steve Hoover
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74d2ba2733
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Tweaks.
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2021-02-16 22:26:22 -05:00 |
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Steve Hoover
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d0860624b7
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Quick fixes.
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2021-02-15 21:55:36 -05:00 |
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Steve Hoover
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b8f6da26d0
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Misc updates.
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2021-02-15 21:49:35 -05:00 |
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Steve Hoover
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b46acf235f
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WIP improvements to RISC-V VIZ, etc.
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2021-02-11 21:18:16 -05:00 |
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Steve Hoover
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f9047e6dc0
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fix
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2021-02-09 19:13:38 -05:00 |
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Steve Hoover
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d3872a0fe1
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Refinements to full_riscv.tlv and copied to lib/risc-v_shell_lib.tlv to serve as reference solution and library.
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2021-02-09 18:22:48 -05:00 |
Shivam Potdar
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dfa3bfe8be
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Update risc-v_shell.tlv
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2021-02-09 19:26:03 +05:30 |
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Steve Hoover
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cd42316a04
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Update risc-v_shell.tlv
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2021-02-08 14:45:26 -05:00 |
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Steve Hoover
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d4492c268b
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Update README.md
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2021-02-08 14:37:13 -05:00 |
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Steve Hoover
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67ea239ec0
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Update risc-v_shell.tlv
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2021-02-08 13:53:03 -05:00 |
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Steve Hoover
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a25f70e45b
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Update README.md
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2021-02-08 13:51:19 -05:00 |
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Steve Hoover
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5165d3a3b8
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Update README.md
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2021-02-08 13:50:44 -05:00 |
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Shivam Potdar
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f206e7a370
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initial - riscv files
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2021-02-08 21:10:43 +05:30 |
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Steve Hoover
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18173c0402
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Added lib/calc_viz.tlv.
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2021-02-04 18:40:58 -05:00 |
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Steve Hoover
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ccd165ac54
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Create README.md
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2021-01-29 11:32:06 -05:00 |