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LF-Building-a-RISC-V-CPU-Core
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67 Commits

Author SHA1 Message Date
Victor Timofei ff0ec641d2
Add data memory and implement store/load 2022-01-16 21:48:31 +02:00
Victor Timofei d2b945d974
Add Jump instructions 2022-01-16 20:36:50 +02:00
Victor Timofei ce288f2840
Merge branch 'stevehoover:main' into main 2022-01-16 19:20:20 +02:00
Victor Timofei c98b2fc672
Complete ALU 2022-01-16 14:22:57 +02:00
Victor Timofei 26bc694325
Fix decoder 2022-01-16 14:22:40 +02:00
Victor Timofei 97e7881dbe
Decode the rest instructions 2022-01-16 12:53:15 +02:00
Steve Hoover dcd5e407e3 \viz_alpha -> \viz_js 
Added $ to missing signals VIZ.
 2022-01-14 15:15:19 -05:00
Steve Hoover dac60392eb \viz_alpha -> \viz_js 2022-01-14 13:25:47 -05:00
Victor Timofei 8fc1626ae3
Change test 2022-01-11 21:58:01 +02:00
Victor Timofei 7085ac35bc
Replace passed check 2022-01-11 21:50:47 +02:00
Victor Timofei 0f3b747dc7
Cleanup bogus use 2022-01-11 21:46:04 +02:00
Victor Timofei 6c08931ddd
Implement branch 2022-01-11 21:44:11 +02:00
Victor Timofei a7d3c26f76
Disable writing to register 0 2022-01-11 21:20:03 +02:00
Victor Timofei 92c9d9c91e
Connect result to write data 2022-01-11 21:18:10 +02:00
Victor Timofei 85eebd8a1b
Add `add` instructions for ALU and disable write 2022-01-11 21:04:31 +02:00
Victor Timofei 432ce28d5d
Add register file 2022-01-11 20:44:57 +02:00
Victor Timofei f6b0d66747
Decode instructions 2022-01-10 23:50:30 +02:00
Victor Timofei be9fe44a80
Extract instruction fields 2022-01-10 23:28:03 +02:00
Victor Timofei 959a2f5eec
Merge branch 'stevehoover:main' into main 2022-01-10 22:07:31 +02:00
Victor Timofei 77577c5d03
Fix binary literal 2022-01-10 22:06:15 +02:00
Victor Timofei 6c05fd21ef
Decode instruction types 2022-01-10 22:04:05 +02:00
Victor Timofei d5bb6da13c
Add instruction memory 2022-01-10 21:19:32 +02:00
Victor Timofei b3412a9706
Add program counter 2022-01-10 21:01:15 +02:00
Steve Hoover 977e7124bb Fix. 2021-12-15 18:41:02 -05:00
Steve Hoover a0a5d1f72c Ignore .bak files. 2021-12-15 18:34:50 -05:00
Steve Hoover 9468717352 Updates for newer Fabric/VIZ. 2021-12-15 18:04:04 -05:00
Steve Hoover 0e71e94d9c Removed bug workaround. 2021-08-26 11:44:43 -04:00
Steve Hoover 9dea12acf9
Delete full_riscv.tlv 
Seems full_riscv.tlv is a leftover file. Solutions should be hidden, and this was incomplete.
 2021-07-28 18:09:27 -04:00
Steve Hoover 0dae4321ff
Update risc-v_solutions.tlv 
Applied a workaround to breaking changes in M4 processing affecting hiding mechanism. These changes are to be reverted once the issue is properly fixed.
 2021-03-28 19:59:52 -04:00
Steve Hoover 378872dede Added banner, course link, and next steps links. 2021-03-01 16:29:27 -05:00
Steve Hoover dbf18f4d36 Updated SVG. 2021-03-01 15:50:23 -05:00
Steve Hoover cd462a8a8d Updated m4+dmem(..) to have a single address argument. 2021-02-28 17:55:15 -05:00
Steve Hoover c2b5ff0171 Providing bit widths on array macro inputs. 2021-02-27 19:05:01 -05:00
Steve Hoover b24f7ea69f Enabled bit-width checking. 2021-02-27 17:03:26 -05:00
Steve Hoover a1b664f8a6 minor. 2021-02-27 15:49:57 -05:00
Steve Hoover d2e0c8cbcf minor. 2021-02-27 15:38:14 -05:00
Steve Hoover 4ed61feeeb Made values hexadecimal in VIZ for full test program. 2021-02-26 20:17:40 -05:00
Steve Hoover 3de301a7ed Test prog macro again needs to define cycle count. 2021-02-26 20:04:24 -05:00
Steve Hoover 4efdd7838c Restored \TLV test_prog() for reference solutions. 2021-02-26 19:56:16 -05:00
Steve Hoover 67042549b7 Reworking the way test_prog works. 2021-02-26 19:42:23 -05:00
Steve Hoover 93d3108a30 Include //m4+test_prog in shell because it must be instantiated in the right place. 2021-02-26 18:33:23 -05:00
Steve Hoover 09f187f917 Allow m4+test_prog after use of M4_MAX_CYC. 2021-02-26 18:27:40 -05:00
Steve Hoover f86204080c Resolving issue with m4_asm_end which must be used from both \TLV and \SV context. 
Use of new signal goTo* functions in VIZ.
Readme updates.
 2021-02-26 17:43:18 -05:00
Steve Hoover 315e5d541a Updated shell code to use x vs. r for regs. 2021-02-17 20:21:21 -05:00
Steve Hoover c3472c5480 Updated from r -> x in decode VIZ. 2021-02-17 20:14:19 -05:00
Steve Hoover 876efb8faa Updated regs to x vs r. 2021-02-17 19:57:32 -05:00
Steve Hoover 62288d1b08 Merge branch 'main' of github.com:stevehoover/LF-Building-a-RISC-V-CPU-Core into main 2021-02-17 19:49:26 -05:00
Steve Hoover e5981f0b05 Update WARP-V to allow xX vs. rX register names. 2021-02-17 19:49:15 -05:00
Steve Hoover 87d119179d
Update README.md 2021-02-17 17:40:39 -05:00
Steve Hoover 42316d6e24
Update README.md 2021-02-17 17:38:52 -05:00