Steve Hoover
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cd462a8a8d
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Updated m4+dmem(..) to have a single address argument.
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2021-02-28 17:55:15 -05:00 |
|
Steve Hoover
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4ed61feeeb
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Made values hexadecimal in VIZ for full test program.
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2021-02-26 20:17:40 -05:00 |
|
Steve Hoover
|
3de301a7ed
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Test prog macro again needs to define cycle count.
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2021-02-26 20:04:24 -05:00 |
|
Steve Hoover
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4efdd7838c
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Restored \TLV test_prog() for reference solutions.
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2021-02-26 19:56:16 -05:00 |
|
Steve Hoover
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67042549b7
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Reworking the way test_prog works.
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2021-02-26 19:42:23 -05:00 |
|
Steve Hoover
|
09f187f917
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Allow m4+test_prog after use of M4_MAX_CYC.
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2021-02-26 18:27:40 -05:00 |
|
Steve Hoover
|
f86204080c
|
Resolving issue with m4_asm_end which must be used from both \TLV and \SV context.
Use of new signal goTo* functions in VIZ.
Readme updates.
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2021-02-26 17:43:18 -05:00 |
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Steve Hoover
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c3472c5480
|
Updated from r -> x in decode VIZ.
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2021-02-17 20:14:19 -05:00 |
|
Steve Hoover
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876efb8faa
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Updated regs to x vs r.
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2021-02-17 19:57:32 -05:00 |
|
Steve Hoover
|
e5981f0b05
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Update WARP-V to allow xX vs. rX register names.
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2021-02-17 19:49:15 -05:00 |
|
Steve Hoover
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aa0e1a756b
|
Prepping shell and reference solutions.
|
2021-02-17 17:33:13 -05:00 |
|
Steve Hoover
|
74d2ba2733
|
Tweaks.
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2021-02-16 22:26:22 -05:00 |
|
Steve Hoover
|
d0860624b7
|
Quick fixes.
|
2021-02-15 21:55:36 -05:00 |
|
Steve Hoover
|
b8f6da26d0
|
Misc updates.
|
2021-02-15 21:49:35 -05:00 |
|
Steve Hoover
|
b46acf235f
|
WIP improvements to RISC-V VIZ, etc.
|
2021-02-11 21:18:16 -05:00 |
|
Steve Hoover
|
f9047e6dc0
|
fix
|
2021-02-09 19:13:38 -05:00 |
|
Steve Hoover
|
d3872a0fe1
|
Refinements to full_riscv.tlv and copied to lib/risc-v_shell_lib.tlv to serve as reference solution and library.
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2021-02-09 18:22:48 -05:00 |
Shivam Potdar
|
f206e7a370
|
initial - riscv files
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2021-02-08 21:10:43 +05:30 |
|
Steve Hoover
|
18173c0402
|
Added lib/calc_viz.tlv.
|
2021-02-04 18:40:58 -05:00 |