 Victor Timofei
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77577c5d03
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Fix binary literal
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2022-01-10 22:06:15 +02:00 |
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Victor Timofei
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6c05fd21ef
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Decode instruction types
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2022-01-10 22:04:05 +02:00 |
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Victor Timofei
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d5bb6da13c
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Add instruction memory
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2022-01-10 21:19:32 +02:00 |
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Victor Timofei
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b3412a9706
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Add program counter
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2022-01-10 21:01:15 +02:00 |
Steve Hoover
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cd462a8a8d
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Updated m4+dmem(..) to have a single address argument.
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2021-02-28 17:55:15 -05:00 |
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Steve Hoover
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c2b5ff0171
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Providing bit widths on array macro inputs.
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2021-02-27 19:05:01 -05:00 |
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Steve Hoover
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b24f7ea69f
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Enabled bit-width checking.
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2021-02-27 17:03:26 -05:00 |
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Steve Hoover
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d2e0c8cbcf
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minor.
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2021-02-27 15:38:14 -05:00 |
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Steve Hoover
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4efdd7838c
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Restored \TLV test_prog() for reference solutions.
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2021-02-26 19:56:16 -05:00 |
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Steve Hoover
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93d3108a30
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Include //m4+test_prog in shell because it must be instantiated in the right place.
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2021-02-26 18:33:23 -05:00 |
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Steve Hoover
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315e5d541a
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Updated shell code to use x vs. r for regs.
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2021-02-17 20:21:21 -05:00 |
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Steve Hoover
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d0860624b7
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Quick fixes.
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2021-02-15 21:55:36 -05:00 |
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Steve Hoover
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b8f6da26d0
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Misc updates.
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2021-02-15 21:49:35 -05:00 |
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Steve Hoover
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b46acf235f
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WIP improvements to RISC-V VIZ, etc.
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2021-02-11 21:18:16 -05:00 |
Shivam Potdar
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dfa3bfe8be
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Update risc-v_shell.tlv
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2021-02-09 19:26:03 +05:30 |
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Steve Hoover
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cd42316a04
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Update risc-v_shell.tlv
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2021-02-08 14:45:26 -05:00 |
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Steve Hoover
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67ea239ec0
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Update risc-v_shell.tlv
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2021-02-08 13:53:03 -05:00 |
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Shivam Potdar
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f206e7a370
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initial - riscv files
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2021-02-08 21:10:43 +05:30 |