33 Commits

Author	SHA1	Message	Date
Victor Timofei	ff0ec641d2	Add data memory and implement store/load	2022-01-16 21:48:31 +02:00
Victor Timofei	d2b945d974	Add Jump instructions	2022-01-16 20:36:50 +02:00
Victor Timofei	c98b2fc672	Complete ALU	2022-01-16 14:22:57 +02:00
Victor Timofei	26bc694325	Fix decoder	2022-01-16 14:22:40 +02:00
Victor Timofei	97e7881dbe	Decode the rest instructions	2022-01-16 12:53:15 +02:00
Victor Timofei	8fc1626ae3	Change test	2022-01-11 21:58:01 +02:00
Victor Timofei	7085ac35bc	Replace passed check	2022-01-11 21:50:47 +02:00
Victor Timofei	0f3b747dc7	Cleanup bogus use	2022-01-11 21:46:04 +02:00
Victor Timofei	6c08931ddd	Implement branch	2022-01-11 21:44:11 +02:00
Victor Timofei	a7d3c26f76	Disable writing to register 0	2022-01-11 21:20:03 +02:00
Victor Timofei	92c9d9c91e	Connect result to write data	2022-01-11 21:18:10 +02:00
Victor Timofei	85eebd8a1b	Add `add` instructions for ALU and disable write	2022-01-11 21:04:31 +02:00
Victor Timofei	432ce28d5d	Add register file	2022-01-11 20:44:57 +02:00
Victor Timofei	f6b0d66747	Decode instructions	2022-01-10 23:50:30 +02:00
Victor Timofei	be9fe44a80	Extract instruction fields	2022-01-10 23:28:03 +02:00
Victor Timofei	77577c5d03	Fix binary literal	2022-01-10 22:06:15 +02:00
Victor Timofei	6c05fd21ef	Decode instruction types	2022-01-10 22:04:05 +02:00
Victor Timofei	d5bb6da13c	Add instruction memory	2022-01-10 21:19:32 +02:00
Victor Timofei	b3412a9706	Add program counter	2022-01-10 21:01:15 +02:00
Steve Hoover	cd462a8a8d	Updated m4+dmem(..) to have a single address argument.	2021-02-28 17:55:15 -05:00
Steve Hoover	c2b5ff0171	Providing bit widths on array macro inputs.	2021-02-27 19:05:01 -05:00
Steve Hoover	b24f7ea69f	Enabled bit-width checking.	2021-02-27 17:03:26 -05:00
Steve Hoover	d2e0c8cbcf	minor.	2021-02-27 15:38:14 -05:00
Steve Hoover	4efdd7838c	Restored \TLV test_prog() for reference solutions.	2021-02-26 19:56:16 -05:00
Steve Hoover	93d3108a30	Include //m4+test_prog in shell because it must be instantiated in the right place.	2021-02-26 18:33:23 -05:00
Steve Hoover	315e5d541a	Updated shell code to use x vs. r for regs.	2021-02-17 20:21:21 -05:00
Steve Hoover	d0860624b7	Quick fixes.	2021-02-15 21:55:36 -05:00
Steve Hoover	b8f6da26d0	Misc updates.	2021-02-15 21:49:35 -05:00
Steve Hoover	b46acf235f	WIP improvements to RISC-V VIZ, etc.	2021-02-11 21:18:16 -05:00
Shivam Potdar	dfa3bfe8be	Update risc-v_shell.tlv	2021-02-09 19:26:03 +05:30
Steve Hoover	cd42316a04	Update risc-v_shell.tlv	2021-02-08 14:45:26 -05:00
Steve Hoover	67ea239ec0	Update risc-v_shell.tlv	2021-02-08 13:53:03 -05:00
Shivam Potdar	f206e7a370	initial - riscv files	2021-02-08 21:10:43 +05:30