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LF-Building-a-RISC-V-CPU-Core
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Update risc-v_shell.tlv

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Shivam Potdar 2021-02-09 19:26:03 +05:30 committed by GitHub
parent cd42316a04
commit dfa3bfe8be
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1 changed files with 10 additions and 16 deletions
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risc-v_shell.tlv
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@ -42,12 +42,7 @@
m4_define_hier(['M4_IMEM'], M4_NUM_INSTRS)
m4+fill_imem()
|cpu
@0
$reset = *reset;
// YOUR CODE HERE
// ...
@ -65,11 +60,10 @@
// o register file
// o data memory
// o CPU visualization
|cpu
m4+rf(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data, $port3_en, $port3_index, $$port3_data)
m4+dmem(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data)
//m4+cpu_viz(@4) // For visualisation, argument should be at least equal to the last stage of CPU logic
// @4 would work for all labs
//m4+rf(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data, $port3_en, $port3_index, $$port3_data)
//m4+dmem(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data)
//m4+cpu_viz() // For visualisation, argument should be at least equal to the last stage of CPU logic
\SV
endmodule