70 lines
2.7 KiB
Plaintext
70 lines
2.7 KiB
Plaintext
\m4_TLV_version 1d: tl-x.org
|
|
\SV
|
|
// This code can be found in: https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/risc-v_shell.tlv
|
|
|
|
m4_include_lib(['https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/main/lib/risc-v_shell_lib.tlv'])
|
|
|
|
\SV
|
|
m4_makerchip_module // (Expanded in Nav-TLV pane.)
|
|
\TLV
|
|
|
|
// /====================\
|
|
// | Sum 1 to 9 Program |
|
|
// \====================/
|
|
//
|
|
// Program for MYTH Workshop to test RV32I
|
|
// Add 1,2,3,...,9 (in that order).
|
|
//
|
|
// Regs:
|
|
// r10 (a0): In: 0, Out: final sum
|
|
// r12 (a2): 10
|
|
// r13 (a3): 1..10
|
|
// r14 (a4): Sum
|
|
//
|
|
// External to function:
|
|
m4_asm(ADD, r10, r0, r0) // Initialize r10 (a0) to 0.
|
|
// Function:
|
|
m4_asm(ADD, r14, r10, r0) // Initialize sum register a4 with 0x0
|
|
m4_asm(ADDI, r12, r10, 1010) // Store count of 10 in register a2.
|
|
m4_asm(ADD, r13, r10, r0) // Initialize intermediate sum register a3 with 0
|
|
// Loop:
|
|
m4_asm(ADD, r14, r13, r14) // Incremental addition
|
|
m4_asm(ADDI, r13, r13, 1) // Increment intermediate register by 1
|
|
m4_asm(BLT, r13, r12, 1111111111000) // If a3 is less than a2, branch to label named <loop>
|
|
m4_asm(ADD, r10, r14, r0) // Store final result to register a0 so that it can be read by main program
|
|
m4_asm(ADDI, r1, r0, 101)
|
|
m4_asm(ORI, r6, r0, 0)
|
|
m4_asm(SW, r6, r1, 0)
|
|
m4_asm(LW, r4, r6, 0)
|
|
|
|
// Optional:
|
|
m4_asm(JAL, r7, 11111111111111101000) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
|
|
m4_define_hier(['M4_IMEM'], M4_NUM_INSTRS)
|
|
m4+fill_imem()
|
|
|
|
$reset = *reset;
|
|
// YOUR CODE HERE
|
|
// ...
|
|
|
|
// Note: Because of the magic we are using for visualisation, if visualisation is enabled below,
|
|
// be sure to avoid having unassigned signals (which you might be using for random inputs)
|
|
// other than those specifically expected in the labs. You'll get strange errors for these.
|
|
|
|
|
|
// Assert these to end simulation (before Makerchip cycle limit).
|
|
*passed = *cyc_cnt > 40;
|
|
*failed = 1'b0;
|
|
|
|
// Macro instantiations for:
|
|
// o instruction memory
|
|
// o register file
|
|
// o data memory
|
|
// o CPU visualization
|
|
|
|
//m4+rf(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data, $port3_en, $port3_index, $$port3_data)
|
|
//m4+dmem(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data)
|
|
|
|
//m4+cpu_viz() // For visualisation, argument should be at least equal to the last stage of CPU logic
|
|
\SV
|
|
endmodule
|