vtimofei
/
LF-Building-a-RISC-V-CPU-Core
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Update risc-v_shell.tlv

This commit is contained in:
Shivam Potdar 2021-02-09 19:26:03 +05:30 committed by GitHub
parent cd42316a04
commit dfa3bfe8be
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 10 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
risc-v_shell.tlv
View File

@ -42,18 +42,13 @@
m4_define_hier(['M4_IMEM'], M4_NUM_INSTRS) m4_define_hier(['M4_IMEM'], M4_NUM_INSTRS)
m4+fill_imem() m4+fill_imem()
|cpu $reset = *reset;
@0 // YOUR CODE HERE
$reset = *reset; // ...
// Note: Because of the magic we are using for visualisation, if visualisation is enabled below,
// be sure to avoid having unassigned signals (which you might be using for random inputs)
// YOUR CODE HERE // other than those specifically expected in the labs. You'll get strange errors for these.
// ...
// Note: Because of the magic we are using for visualisation, if visualisation is enabled below,
// be sure to avoid having unassigned signals (which you might be using for random inputs)
// other than those specifically expected in the labs. You'll get strange errors for these.
// Assert these to end simulation (before Makerchip cycle limit). // Assert these to end simulation (before Makerchip cycle limit).
@ -65,11 +60,10 @@
// o register file // o register file
// o data memory // o data memory
// o CPU visualization // o CPU visualization
|cpu
m4+rf(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data, $port3_en, $port3_index, $$port3_data)
m4+dmem(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data)
//m4+cpu_viz(@4) // For visualisation, argument should be at least equal to the last stage of CPU logic //m4+rf(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data, $port3_en, $port3_index, $$port3_data)
// @4 would work for all labs //m4+dmem(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data)
//m4+cpu_viz() // For visualisation, argument should be at least equal to the last stage of CPU logic
\SV \SV
endmodule endmodule