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LF-Building-a-RISC-V-CPU-Core
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Add register file

This commit is contained in:
Victor Timofei 2022-01-11 20:44:57 +02:00
parent f6b0d66747
commit 432ce28d5d
Signed by: vtimofei
GPG Key ID: B790DCEBE281403A
1 changed files with 2 additions and 1 deletions
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risc-v_shell.tlv
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@ -103,7 +103,8 @@
*passed = 1'b0; *passed = 1'b0;
*failed = *cyc_cnt > M4_MAX_CYC; *failed = *cyc_cnt > M4_MAX_CYC;
//m4+rf(32, 32, $reset, $wr_en, $wr_index[4:0], $wr_data[31:0], $rd1_en, $rd1_index[4:0], $rd1_data, $rd2_en, $rd2_index[4:0], $rd2_data) // Register file
m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $wr_data[31:0], $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
//m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data) //m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
m4+cpu_viz() m4+cpu_viz()
\SV \SV