From 432ce28d5d174720848b1932334b66c3ef31a0b6 Mon Sep 17 00:00:00 2001
From: Victor Timofei <victor@vtimothy.com>
Date: Tue, 11 Jan 2022 20:44:57 +0200
Subject: [PATCH] Add register file

---
 risc-v_shell.tlv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/risc-v_shell.tlv b/risc-v_shell.tlv
index 0a81eab..865273e 100644
--- a/risc-v_shell.tlv
+++ b/risc-v_shell.tlv
@@ -103,7 +103,8 @@
    *passed = 1'b0;
    *failed = *cyc_cnt > M4_MAX_CYC;
 
-   //m4+rf(32, 32, $reset, $wr_en, $wr_index[4:0], $wr_data[31:0], $rd1_en, $rd1_index[4:0], $rd1_data, $rd2_en, $rd2_index[4:0], $rd2_data)
+   // Register file
+   m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $wr_data[31:0], $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
    //m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
    m4+cpu_viz()
 \SV