112 lines
4.4 KiB
Plaintext
112 lines
4.4 KiB
Plaintext
\m4_TLV_version 1d: tl-x.org
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\SV
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// This code can be found in: https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/risc-v_shell.tlv
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m4_include_lib(['https://raw.githubusercontent.com/stevehoover/warp-v_includes/1d1023ccf8e7b0a8cf8e8fc4f0a823ebb61008e3/risc-v_defs.tlv'])
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m4_include_lib(['https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/main/lib/risc-v_shell_lib.tlv'])
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//---------------------------------------------------------------------------------
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// /====================\
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// | Sum 1 to 9 Program |
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// \====================/
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//
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// Program to test RV32I
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// Add 1,2,3,...,9 (in that order).
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//
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// Regs:
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// x12 (a2): 10
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// x13 (a3): 1..10
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// x14 (a4): Sum
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//
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m4_asm(ADDI, x14, x0, 0) // Initialize sum register a4 with 0
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m4_asm(ADDI, x12, x0, 1010) // Store count of 10 in register a2.
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m4_asm(ADDI, x13, x0, 1) // Initialize loop count register a3 with 0
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// Loop:
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m4_asm(ADD, x14, x13, x14) // Incremental summation
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m4_asm(ADDI, x13, x13, 1) // Increment loop count by 1
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m4_asm(BLT, x13, x12, 1111111111000) // If a3 is less than a2, branch to label named <loop>
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// Test result value in x14, and set x31 to reflect pass/fail.
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m4_asm(ADDI, x30, x14, 111111010100) // Subtract expected value of 44 to set x30 to 1 if and only iff the result is 45 (1 + 2 + ... + 9).
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m4_asm(BGE, x0, x0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
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m4_asm_end()
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m4_define(['M4_MAX_CYC'], 50)
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//---------------------------------------------------------------------------------
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\SV
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m4_makerchip_module // (Expanded in Nav-TLV pane.)
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/* verilator lint_on WIDTH */
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\TLV
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$reset = *reset;
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// Program counter
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$next_pc[31:0] = $reset ? 0 : ($pc + 4);
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$pc[31:0] = >>1$next_pc;
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// Instruction memory
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`READONLY_MEM($pc, $$instr[31:0]);
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// Decode instruction types
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$is_u_instr = $instr[6:2] ==? 5'b0x101;
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$is_i_instr = $instr[6:2] ==? 5'b0000x
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|| $instr[6:2] ==? 5'b001x0
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|| $instr[6:2] == 5'b11001;
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$is_r_instr = $instr[6:2] ==? 5'b011x0
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|| $instr[6:2] == 5'b01011
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|| $instr[6:2] == 5'b10100;
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$is_s_instr = $instr[6:2] ==? 5'b0100x;
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$is_b_instr = $instr[6:2] == 5'b11000;
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$is_j_instr = $instr[6:2] == 5'b11011;
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// Extract instruction fields
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$func3[2:0] = $instr[14:12];
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$rs2[4:0] = $instr[24:20];
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$rs1[4:0] = $instr[19:15];
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$rd[4:0] = $instr[11:7];
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$opcode[6:0] = $instr[6:0];
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$func3_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
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$rs2_valid = $is_r_instr || $is_s_instr || $is_b_instr;
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$rs1_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
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$rd_valid = $is_r_instr || $is_i_instr || $is_u_instr || $is_j_instr;
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$imm_valid = $is_i_instr || $is_s_instr || $is_b_instr || $is_u_instr || $is_j_instr;
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`BOGUS_USE($rd $rd_valid $rs1 $rs1_valid $rs2 $rs2_valid $func3 $func3_valid $imm_valid $opcode)
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$imm[31:0] = $is_i_instr ? { {21{$instr[31]}}, $instr[30:20] } :
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$is_s_instr ? { {21{$instr[31]}}, $instr[30:25], $instr[11:7] } :
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$is_b_instr ? { {20{$instr[31]}}, $instr[7], $instr[30:25], $instr[11:8], 1'b0 } :
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$is_u_instr ? { $instr[31], $instr[30:12], 12'b0 } :
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$is_j_instr ? { {12{$instr[31]}}, $instr[19:12], $instr[20], $instr[30:21], 1'b0 } :
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32'b0;
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// Decode instructions
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$dec_bits[10:0] = {$instr[30], $func3, $opcode};
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$is_beq = $dec_bits ==? 11'bx_000_110_0011;
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$is_bne = $dec_bits ==? 11'bx_001_110_0011;
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$is_blt = $dec_bits ==? 11'bx_100_110_0011;
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$is_bge = $dec_bits ==? 11'bx_101_110_0011;
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$is_bltu = $dec_bits ==? 11'bx_110_110_0011;
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$is_bgeu = $dec_bits ==? 11'bx_111_110_0011;
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$is_addi = $dec_bits ==? 11'bx_000_001_0011;
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$is_add = $dec_bits == 11'b0_000_011_0011;
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`BOGUS_USE($imm $is_beq $is_bne $is_blt $is_bge $is_bltu $is_bgeu $is_addi $is_add)
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// Assert these to end simulation (before Makerchip cycle limit).
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*passed = 1'b0;
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*failed = *cyc_cnt > M4_MAX_CYC;
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// Register file
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m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $wr_data[31:0], $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
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//m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
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m4+cpu_viz()
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\SV
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endmodule
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