vtimofei
/
LF-Building-a-RISC-V-CPU-Core
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
21 Commits 1 Branch 0 Tags 272 KiB
SVG 100%
Go to file
Steve Hoover 62288d1b08 Merge branch 'main' of github.com:stevehoover/LF-Building-a-RISC-V-CPU-Core into main 2021-02-17 19:49:26 -05:00
lib Update WARP-V to allow xX vs. rX register names. 2021-02-17 19:49:15 -05:00
README.md Update README.md 2021-02-17 17:40:39 -05:00
full_riscv.tlv Misc updates. 2021-02-15 21:49:35 -05:00
risc-v_shell.tlv Quick fixes. 2021-02-15 21:55:36 -05:00
risc-v_solutions.tlv Prepping shell and reference solutions. 2021-02-17 17:33:13 -05:00

README.md

Building a RISC-V CPU Core

Accompanying resources for the Building a RISC-V CPU Core EdX course by Steve Hoover of Redwood EDA, Linux Foundation, and RISC-V International.

RISC-V Starting-Point Code

To begin the first RISC-V lab, Ctrl-click this link to open starting-point code in makerchip.

RISC-V Reference Solution

In case you get stuck, we've got your back! These reference solutions (Ctrl-click) will help with syntax, etc. without handing your the answers.

Final Result

Final Core