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LF-Building-a-RISC-V-CPU-Core
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Decode instructions

This commit is contained in:
Victor Timofei 2022-01-10 23:50:30 +02:00
parent be9fe44a80
commit f6b0d66747
Signed by: vtimofei
GPG Key ID: B790DCEBE281403A
1 changed files with 24 additions and 10 deletions
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14
risc-v_shell.tlv
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@ -85,6 +85,20 @@
$is_j_instr ? { {12{$instr[31]}}, $instr[19:12], $instr[20], $instr[30:21], 1'b0 } :
32'b0;
// Decode instructions
$dec_bits[10:0] = {$instr[30], $func3, $opcode};
$is_beq = $dec_bits ==? 11'bx_000_110_0011;
$is_bne = $dec_bits ==? 11'bx_001_110_0011;
$is_blt = $dec_bits ==? 11'bx_100_110_0011;
$is_bge = $dec_bits ==? 11'bx_101_110_0011;
$is_bltu = $dec_bits ==? 11'bx_110_110_0011;
$is_bgeu = $dec_bits ==? 11'bx_111_110_0011;
$is_addi = $dec_bits ==? 11'bx_000_001_0011;
$is_add = $dec_bits == 11'b0_000_011_0011;
`BOGUS_USE($imm $is_beq $is_bne $is_blt $is_bge $is_bltu $is_bgeu $is_addi $is_add)
// Assert these to end simulation (before Makerchip cycle limit).
*passed = 1'b0;
*failed = *cyc_cnt > M4_MAX_CYC;