From f6b0d66747cd2675d11648579a6b0d2c3fe50288 Mon Sep 17 00:00:00 2001
From: Victor Timofei <victor@vtimothy.com>
Date: Mon, 10 Jan 2022 23:50:30 +0200
Subject: [PATCH] Decode instructions

---
 risc-v_shell.tlv | 34 ++++++++++++++++++++++++----------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/risc-v_shell.tlv b/risc-v_shell.tlv
index 3d4d4dc..0a81eab 100644
--- a/risc-v_shell.tlv
+++ b/risc-v_shell.tlv
@@ -40,17 +40,17 @@
    m4_makerchip_module   // (Expanded in Nav-TLV pane.)
    /* verilator lint_on WIDTH */
 \TLV
-   
+
    $reset = *reset;
-   
-   
+
+
    // Program counter
    $next_pc[31:0] = $reset ? 0 : ($pc + 4);
    $pc[31:0] = >>1$next_pc;
 
    // Instruction memory
    `READONLY_MEM($pc, $$instr[31:0]);
-   
+
    // Decode instruction types
    $is_u_instr = $instr[6:2] ==? 5'b0x101;
    $is_i_instr = $instr[6:2] ==? 5'b0000x
@@ -62,33 +62,47 @@
    $is_s_instr = $instr[6:2] ==? 5'b0100x;
    $is_b_instr = $instr[6:2] == 5'b11000;
    $is_j_instr = $instr[6:2] == 5'b11011;
-   
+
    // Extract instruction fields
    $func3[2:0] = $instr[14:12];
    $rs2[4:0] = $instr[24:20];
    $rs1[4:0] = $instr[19:15];
    $rd[4:0] = $instr[11:7];
    $opcode[6:0] = $instr[6:0];
-   
+
    $func3_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
    $rs2_valid = $is_r_instr || $is_s_instr || $is_b_instr;
    $rs1_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
    $rd_valid = $is_r_instr || $is_i_instr || $is_u_instr || $is_j_instr;
    $imm_valid = $is_i_instr || $is_s_instr || $is_b_instr || $is_u_instr || $is_j_instr;
-   
+
    `BOGUS_USE($rd $rd_valid $rs1 $rs1_valid $rs2 $rs2_valid $func3 $func3_valid $imm_valid $opcode)
-   
+
    $imm[31:0] = $is_i_instr ? { {21{$instr[31]}}, $instr[30:20] } :
       $is_s_instr ? { {21{$instr[31]}}, $instr[30:25], $instr[11:7] } :
       $is_b_instr ? { {20{$instr[31]}}, $instr[7], $instr[30:25], $instr[11:8], 1'b0 } :
       $is_u_instr ? { $instr[31], $instr[30:12], 12'b0 } :
       $is_j_instr ? { {12{$instr[31]}}, $instr[19:12], $instr[20], $instr[30:21], 1'b0 } :
       32'b0;
-   
+
+   // Decode instructions
+   $dec_bits[10:0] = {$instr[30], $func3, $opcode};
+
+   $is_beq = $dec_bits ==? 11'bx_000_110_0011;
+   $is_bne = $dec_bits ==? 11'bx_001_110_0011;
+   $is_blt = $dec_bits ==? 11'bx_100_110_0011;
+   $is_bge = $dec_bits ==? 11'bx_101_110_0011;
+   $is_bltu = $dec_bits ==? 11'bx_110_110_0011;
+   $is_bgeu = $dec_bits ==? 11'bx_111_110_0011;
+   $is_addi = $dec_bits ==? 11'bx_000_001_0011;
+   $is_add = $dec_bits == 11'b0_000_011_0011;
+
+   `BOGUS_USE($imm $is_beq $is_bne $is_blt $is_bge $is_bltu $is_bgeu $is_addi $is_add)
+
    // Assert these to end simulation (before Makerchip cycle limit).
    *passed = 1'b0;
    *failed = *cyc_cnt > M4_MAX_CYC;
-   
+
    //m4+rf(32, 32, $reset, $wr_en, $wr_index[4:0], $wr_data[31:0], $rd1_en, $rd1_index[4:0], $rd1_data, $rd2_en, $rd2_index[4:0], $rd2_data)
    //m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
    m4+cpu_viz()