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LF-Building-a-RISC-V-CPU-Core
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Decode instructions

This commit is contained in:
Victor Timofei 2022-01-10 23:50:30 +02:00
parent be9fe44a80
commit f6b0d66747
Signed by: vtimofei
GPG Key ID: B790DCEBE281403A
1 changed files with 24 additions and 10 deletions
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34
risc-v_shell.tlv
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@ -40,17 +40,17 @@
m4_makerchip_module // (Expanded in Nav-TLV pane.) m4_makerchip_module // (Expanded in Nav-TLV pane.)
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
\TLV \TLV
$reset = *reset; $reset = *reset;
// Program counter // Program counter
$next_pc[31:0] = $reset ? 0 : ($pc + 4); $next_pc[31:0] = $reset ? 0 : ($pc + 4);
$pc[31:0] = >>1$next_pc; $pc[31:0] = >>1$next_pc;
// Instruction memory // Instruction memory
`READONLY_MEM($pc, $$instr[31:0]); `READONLY_MEM($pc, $$instr[31:0]);
// Decode instruction types // Decode instruction types
$is_u_instr = $instr[6:2] ==? 5'b0x101; $is_u_instr = $instr[6:2] ==? 5'b0x101;
$is_i_instr = $instr[6:2] ==? 5'b0000x $is_i_instr = $instr[6:2] ==? 5'b0000x
@ -62,33 +62,47 @@
$is_s_instr = $instr[6:2] ==? 5'b0100x; $is_s_instr = $instr[6:2] ==? 5'b0100x;
$is_b_instr = $instr[6:2] == 5'b11000; $is_b_instr = $instr[6:2] == 5'b11000;
$is_j_instr = $instr[6:2] == 5'b11011; $is_j_instr = $instr[6:2] == 5'b11011;
// Extract instruction fields // Extract instruction fields
$func3[2:0] = $instr[14:12]; $func3[2:0] = $instr[14:12];
$rs2[4:0] = $instr[24:20]; $rs2[4:0] = $instr[24:20];
$rs1[4:0] = $instr[19:15]; $rs1[4:0] = $instr[19:15];
$rd[4:0] = $instr[11:7]; $rd[4:0] = $instr[11:7];
$opcode[6:0] = $instr[6:0]; $opcode[6:0] = $instr[6:0];
$func3_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr; $func3_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
$rs2_valid = $is_r_instr || $is_s_instr || $is_b_instr; $rs2_valid = $is_r_instr || $is_s_instr || $is_b_instr;
$rs1_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr; $rs1_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
$rd_valid = $is_r_instr || $is_i_instr || $is_u_instr || $is_j_instr; $rd_valid = $is_r_instr || $is_i_instr || $is_u_instr || $is_j_instr;
$imm_valid = $is_i_instr || $is_s_instr || $is_b_instr || $is_u_instr || $is_j_instr; $imm_valid = $is_i_instr || $is_s_instr || $is_b_instr || $is_u_instr || $is_j_instr;
`BOGUS_USE($rd $rd_valid $rs1 $rs1_valid $rs2 $rs2_valid $func3 $func3_valid $imm_valid $opcode) `BOGUS_USE($rd $rd_valid $rs1 $rs1_valid $rs2 $rs2_valid $func3 $func3_valid $imm_valid $opcode)
$imm[31:0] = $is_i_instr ? { {21{$instr[31]}}, $instr[30:20] } : $imm[31:0] = $is_i_instr ? { {21{$instr[31]}}, $instr[30:20] } :
$is_s_instr ? { {21{$instr[31]}}, $instr[30:25], $instr[11:7] } : $is_s_instr ? { {21{$instr[31]}}, $instr[30:25], $instr[11:7] } :
$is_b_instr ? { {20{$instr[31]}}, $instr[7], $instr[30:25], $instr[11:8], 1'b0 } : $is_b_instr ? { {20{$instr[31]}}, $instr[7], $instr[30:25], $instr[11:8], 1'b0 } :
$is_u_instr ? { $instr[31], $instr[30:12], 12'b0 } : $is_u_instr ? { $instr[31], $instr[30:12], 12'b0 } :
$is_j_instr ? { {12{$instr[31]}}, $instr[19:12], $instr[20], $instr[30:21], 1'b0 } : $is_j_instr ? { {12{$instr[31]}}, $instr[19:12], $instr[20], $instr[30:21], 1'b0 } :
32'b0; 32'b0;
// Decode instructions
$dec_bits[10:0] = {$instr[30], $func3, $opcode};
$is_beq = $dec_bits ==? 11'bx_000_110_0011;
$is_bne = $dec_bits ==? 11'bx_001_110_0011;
$is_blt = $dec_bits ==? 11'bx_100_110_0011;
$is_bge = $dec_bits ==? 11'bx_101_110_0011;
$is_bltu = $dec_bits ==? 11'bx_110_110_0011;
$is_bgeu = $dec_bits ==? 11'bx_111_110_0011;
$is_addi = $dec_bits ==? 11'bx_000_001_0011;
$is_add = $dec_bits == 11'b0_000_011_0011;
`BOGUS_USE($imm $is_beq $is_bne $is_blt $is_bge $is_bltu $is_bgeu $is_addi $is_add)
// Assert these to end simulation (before Makerchip cycle limit). // Assert these to end simulation (before Makerchip cycle limit).
*passed = 1'b0; *passed = 1'b0;
*failed = *cyc_cnt > M4_MAX_CYC; *failed = *cyc_cnt > M4_MAX_CYC;
//m4+rf(32, 32, $reset, $wr_en, $wr_index[4:0], $wr_data[31:0], $rd1_en, $rd1_index[4:0], $rd1_data, $rd2_en, $rd2_index[4:0], $rd2_data) //m4+rf(32, 32, $reset, $wr_en, $wr_index[4:0], $wr_data[31:0], $rd1_en, $rd1_index[4:0], $rd1_data, $rd2_en, $rd2_index[4:0], $rd2_data)
//m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data) //m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
m4+cpu_viz() m4+cpu_viz()