\viz_alpha -> \viz_js
This commit is contained in:
Steve Hoover
parent
977e7124bb
commit
dac60392eb
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@ -142,11 +142,9 @@ m4+definitions(['
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$_port3_data[_width-1:0] = $rf1_rd_en2 ? /xreg[$rf1_rd_index2]$value : 'X;
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/xreg[m4_eval(_entries-1):0]
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\viz_alpha
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initEach: function() {
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return {} // {objects: {reg: reg}};
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},
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renderEach: function() {
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\viz_js
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box: {width: 120, height: 18, strokeWidth: 0},
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render() {
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siggen = (name) => this.svSigRef(`${name}`) == null ? this.svSigRef(`sticky_zero`) : this.svSigRef(`${name}`);
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let rf_rd_en1 = siggen(`L0_rf1_rd_en1_a0`)
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@ -165,8 +163,8 @@ m4+definitions(['
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let regIdent = reg.toString().padEnd(2, " ")
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let newValStr = (regIdent + ": ").padEnd(14, " ")
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let reg_str = new fabric.Text((regIdent + ": " + value.asInt(NaN).toString(M4_VIZ_BASE)).padEnd(14, " "), {
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top: 18 * this.getIndex() - 40,
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left: 316,
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top: 0,
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left: 0,
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fontSize: 14,
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fill: mod ? "blue" : "black",
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fontWeight: mod ? 800 : 400,
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@ -179,8 +177,9 @@ m4+definitions(['
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this.global.canvas.renderAll()
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}, 1500)
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}
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return {objects: [reg_str]}
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}
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return [reg_str]
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},
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where: {left: 316, top: -40}
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// Data Memory
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\TLV dmem(_entries, _width, $_reset, $_addr, $_port1_en, $_port1_data, $_port2_en, $_port2_data)
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@ -199,11 +198,9 @@ m4+definitions(['
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$_port2_data[_width-1:0] = $dmem1_rd_en ? /dmem[$dmem1_addr]$value : 'X;
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/dmem[m4_eval(_entries-1):0]
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\viz_alpha
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initEach: function() {
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return {} // {objects: {reg: reg}};
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},
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renderEach: function() {
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\viz_js
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box: {width: 120, height: 18, strokeWidth: 0},
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render() {
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siggen = (name) => this.svSigRef(`${name}`) == null ? this.svSigRef(`sticky_zero`) : this.svSigRef(`${name}`);
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//
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let dmem_rd_en = siggen(`L0_dmem1_rd_en_a0`);
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@ -218,8 +215,8 @@ m4+definitions(['
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let regIdent = reg.toString().padEnd(2, " ");
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let newValStr = (regIdent + ": ").padEnd(14, " ");
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let dmem_str = new fabric.Text((regIdent + ": " + value.asInt(NaN).toString(M4_VIZ_BASE)).padEnd(14, " "), {
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top: 18 * this.getIndex() - 40,
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left: 480,
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top: 0,
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left: 0,
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fontSize: 14,
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fill: mod ? "blue" : "black",
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fontWeight: mod ? 800 : 400,
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@ -232,8 +229,9 @@ m4+definitions(['
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this.global.canvas.renderAll()
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}, 1500)
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}
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return {objects: [dmem_str]}
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}
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return [dmem_str]
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},
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where: {left: 480, top: -40}
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\TLV cpu_viz()
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// String representations of the instructions for debug.
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@ -245,10 +243,10 @@ m4+definitions(['
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logic [40*8-1:0] instr_strs [0:M4_NUM_INSTRS];
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assign instr_strs = '{m4_asm_mem_expr "END "};
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/cpuviz
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\viz_alpha
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\viz_js
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m4_define(['M4_IMEM_TOP'], ['m4_ifelse(m4_eval(M4_NUM_INSTRS > 16), 0, 0, m4_eval(0 - (M4_NUM_INSTRS - 16) * 18))'])
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initEach() {
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box: {strokeWidth: 0},
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init() {
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let imem_box = new fabric.Rect({
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top: M4_IMEM_TOP - 50,
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left: -700,
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@ -328,7 +326,7 @@ m4+definitions(['
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fontSize: 46,
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fontWeight: 800
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})
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let missing_col1 = new fabric.Text("", {
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this.missing_col1 = new fabric.Text("", {
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top: 420,
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left: -480,
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fontSize: 16,
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@ -336,7 +334,7 @@ m4+definitions(['
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fontFamily: "monospace",
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fill: "purple"
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})
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let missing_col2 = new fabric.Text("", {
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this.missing_col2 = new fabric.Text("", {
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top: 420,
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left: -300,
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fontSize: 16,
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@ -361,15 +359,14 @@ m4+definitions(['
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height: 300,
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stroke: "black"
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}),
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missing_col1,
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missing_col2,
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this.missing_col1,
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this.missing_col2,
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],
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{visible: false}
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)
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return {missing_col1, missing_col2,
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objects: {imem_box, decode_box, rf_box, dmem_box, imem_header, decode_header, rf_header, dmem_header, passed, missing_sigs}};
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return {imem_box, decode_box, rf_box, dmem_box, imem_header, decode_header, rf_header, dmem_header, passed, missing_sigs}
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},
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renderEach() {
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render() {
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// Strings (2 columns) of missing signals.
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var missing_list = ["", ""]
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var missing_cnt = 0
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@ -439,10 +436,10 @@ m4+definitions(['
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let dmem_addr = siggen_rf_dmem("dmem1_addr")
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if (instr != sticky_zero) {
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this.getInitObjects().imem_box.setVisible(true)
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this.getInitObjects().imem_header.setVisible(true)
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this.getInitObjects().decode_box.setVisible(true)
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this.getInitObjects().decode_header.setVisible(true)
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this.getObjects().imem_box.set({visible: true})
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this.getObjects().imem_header.set({visible: true})
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this.getObjects().decode_box.set({visible: true})
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this.getObjects().decode_header.set({visible: true})
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}
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let pcPointer = new fabric.Text("👉", {
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top: M4_IMEM_TOP + 18 * (pc.asInt() / 4),
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@ -499,12 +496,12 @@ m4+definitions(['
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visible: dmem_wr_en.asBool()
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})
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if (rf_rd_en1 != sticky_zero) {
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this.getInitObjects().rf_box.setVisible(true)
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this.getInitObjects().rf_header.setVisible(true)
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this.getObjects().rf_box.set({visible: true})
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this.getObjects().rf_header.set({visible: true})
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}
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if (dmem_rd_en != sticky_zero) {
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this.getInitObjects().dmem_box.setVisible(true)
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this.getInitObjects().dmem_header.setVisible(true)
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this.getObjects().dmem_box.set({visible: true})
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this.getObjects().dmem_header.set({visible: true})
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}
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@ -591,13 +588,13 @@ m4+definitions(['
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})
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if (dmem_rd_en.asBool()) {
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setTimeout(() => {
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load_viz.setVisible(true)
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load_viz.set({visible: true})
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load_viz.animate({left: 146, top: 70}, {
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onChange: this.global.canvas.renderAll.bind(this.global.canvas),
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duration: 500
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})
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setTimeout(() => {
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load_viz.setVisible(false)
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load_viz.set({visible: false})
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}, 500)
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}, 500)
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}
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@ -613,7 +610,7 @@ m4+definitions(['
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})
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if (dmem_wr_en.asBool()) {
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setTimeout(() => {
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store_viz.setVisible(true)
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store_viz.set({visible: true})
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store_viz.animate({left: 515, top: 18 * dmem_addr.asInt() - 40}, {
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onChange: this.global.canvas.renderAll.bind(this.global.canvas),
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duration: 500
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@ -641,8 +638,8 @@ m4+definitions(['
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})
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if (rd_valid.asBool()) {
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setTimeout(() => {
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result_viz.setVisible(rf_wr_data != sticky_zero && rf_wr_en.asBool())
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result_shadow.setVisible(result != sticky_zero)
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result_viz.set({visible: rf_wr_data != sticky_zero && rf_wr_en.asBool()})
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result_shadow.set({visible: result != sticky_zero})
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result_viz.animate({left: 317 + 8 * 4, top: 18 * rf_wr_index.asInt(0) - 40}, {
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onChange: this.global.canvas.renderAll.bind(this.global.canvas),
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duration: 500
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@ -653,16 +650,16 @@ m4+definitions(['
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// Lab completion
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// Passed?
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this.getInitObject("passed").setVisible(false)
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this.getObjects().passed.set({visible: false})
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if (passed) {
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if (passed.step(-1).asBool()) {
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this.getInitObject("passed").set({visible: true, text:"Passed !!!", fill: "green"})
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this.getObjects().passed.set({visible: true, text:"Passed !!!", fill: "green"})
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} else {
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// Using an unstable API, so:
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try {
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passed.goToSimEnd().step(-1)
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if (passed.asBool()) {
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this.getInitObject("passed").set({text:"Sim Passes", visible: true, fill: "lightgray"})
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this.getObjects().passed.set({text:"Sim Passes", visible: true, fill: "lightgray"})
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}
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} catch(e) {
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}
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@ -671,57 +668,54 @@ m4+definitions(['
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// Missing signals
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if (missing_list[0]) {
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this.getInitObject("missing_sigs").setVisible(true)
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this.fromInit().missing_col1.set({text: missing_list[0]})
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this.fromInit().missing_col2.set({text: missing_list[1]})
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this.getObjects().missing_sigs.set({visible: true})
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this.missing_col1.set({text: missing_list[0]})
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this.missing_col2.set({text: missing_list[1]})
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}
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return {objects: [pcPointer, pc_arrow, ...type_texts, rs1_arrow, rs2_arrow, rd_arrow, instrWithValues, fetch_instr_viz, src1_value_viz, src2_value_viz, result_shadow, result_viz, ld_arrow, st_arrow, load_viz, store_viz]};
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return [pcPointer, pc_arrow, ...type_texts, rs1_arrow, rs2_arrow, rd_arrow, instrWithValues, fetch_instr_viz, src1_value_viz, src2_value_viz, result_shadow, result_viz, ld_arrow, st_arrow, load_viz, store_viz]
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}
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/imem[m4_eval(M4_NUM_INSTRS-1):0]
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\viz_alpha
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initEach() {
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\viz_js
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box: {width: 630, height: 18, strokeWidth: 0},
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init() {
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let binary = new fabric.Text("", {
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top: M4_IMEM_TOP + 18 * this.getIndex(),
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left: -680,
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top: 0,
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left: 0,
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fontSize: 14,
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fontFamily: "monospace",
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})
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let disassembled = new fabric.Text("", {
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top: M4_IMEM_TOP + 18 * this.getIndex(),
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left: -350,
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top: 0,
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left: 330,
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fontSize: 14,
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fontFamily: "monospace"
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})
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return {objects: {binary, disassembled}}
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return {binary, disassembled}
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},
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renderEach() {
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// Instruction memory is constant, so just create it once.
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let reset = this.svSigRef(`L0_reset_a0`)
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let pc = this.svSigRef(`L0_pc_a0`)
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let rd_viz = pc && !reset.asBool() && (pc.asInt() >> 2) == this.getIndex()
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if (!global.instr_mem_drawn) {
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global.instr_mem_drawn = []
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}
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if (!global.instr_mem_drawn[this.getIndex()]) {
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global.instr_mem_drawn[this.getIndex()] = true
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onTraceData() {
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let instr = this.svSigRef(`instrs(${this.getIndex()})`)
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if (instr) {
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let binary_str = instr.goToSimStart().asBinaryStr("")
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this.getInitObject("binary").set({text: binary_str})
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this.getObjects().binary.set({text: binary_str})
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}
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let disassembled = this.svSigRef(`instr_strs(${this.getIndex()})`)
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if (disassembled) {
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let disassembled_str = disassembled.goToSimStart().asString("")
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disassembled_str = disassembled_str.slice(0, -5)
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this.getInitObject("disassembled").set({text: disassembled_str})
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}
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}
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this.getInitObject("disassembled").set({textBackgroundColor: rd_viz ? "#b0ffff" : "white"})
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this.getInitObject("binary") .set({textBackgroundColor: rd_viz ? "#b0ffff" : "white"})
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this.getObjects().disassembled.set({text: disassembled_str})
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}
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},
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render() {
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// Instruction memory is constant, so just create it once.
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let reset = this.svSigRef(`L0_reset_a0`)
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let pc = this.svSigRef(`L0_pc_a0`)
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let rd_viz = pc && !reset.asBool() && (pc.asInt() >> 2) == this.getIndex()
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this.getObjects().disassembled.set({textBackgroundColor: rd_viz ? "#b0ffff" : "white"})
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this.getObjects().binary .set({textBackgroundColor: rd_viz ? "#b0ffff" : "white"})
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},
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where: {left: -680, top: M4_IMEM_TOP}
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\TLV tb()
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$passed_cond = (/xreg[30]$value == 32'b1) &&
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