Add instruction memory

2022-01-10 21:19:32 +02:00 · 2022-01-10 21:19:32 +02:00 · d5bb6da13c
parent b3412a9706
commit d5bb6da13c
1 changed files with 2 additions and 0 deletions
--- a/risc-v_shell.tlv
+++ b/risc-v_shell.tlv
@ -50,6 +50,8 @@

   $pc[31:0] = >>1$next_pc;

+   `READONLY_MEM($pc, $$instr[31:0]);
+   
   
   // Assert these to end simulation (before Makerchip cycle limit).
   *passed = 1'b0;