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LF-Building-a-RISC-V-CPU-Core
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Add instruction memory

This commit is contained in:
Victor Timofei 2022-01-10 21:19:32 +02:00
parent b3412a9706
commit d5bb6da13c
Signed by: vtimofei
GPG Key ID: B790DCEBE281403A
1 changed files with 2 additions and 0 deletions
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2
risc-v_shell.tlv
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@ -50,6 +50,8 @@
$pc[31:0] = >>1$next_pc; $pc[31:0] = >>1$next_pc;
`READONLY_MEM($pc, $$instr[31:0]);
// Assert these to end simulation (before Makerchip cycle limit). // Assert these to end simulation (before Makerchip cycle limit).
*passed = 1'b0; *passed = 1'b0;