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LF-Building-a-RISC-V-CPU-Core
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Extract instruction fields

This commit is contained in:
Victor Timofei 2022-01-10 23:28:03 +02:00
parent 959a2f5eec
commit be9fe44a80
Signed by: vtimofei
GPG Key ID: B790DCEBE281403A
1 changed files with 22 additions and 0 deletions
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risc-v_shell.tlv
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@ -63,6 +63,28 @@
$is_b_instr = $instr[6:2] == 5'b11000; $is_b_instr = $instr[6:2] == 5'b11000;
$is_j_instr = $instr[6:2] == 5'b11011; $is_j_instr = $instr[6:2] == 5'b11011;
// Extract instruction fields
$func3[2:0] = $instr[14:12];
$rs2[4:0] = $instr[24:20];
$rs1[4:0] = $instr[19:15];
$rd[4:0] = $instr[11:7];
$opcode[6:0] = $instr[6:0];
$func3_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
$rs2_valid = $is_r_instr || $is_s_instr || $is_b_instr;
$rs1_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
$rd_valid = $is_r_instr || $is_i_instr || $is_u_instr || $is_j_instr;
$imm_valid = $is_i_instr || $is_s_instr || $is_b_instr || $is_u_instr || $is_j_instr;
`BOGUS_USE($rd $rd_valid $rs1 $rs1_valid $rs2 $rs2_valid $func3 $func3_valid $imm_valid $opcode)
$imm[31:0] = $is_i_instr ? { {21{$instr[31]}}, $instr[30:20] } :
$is_s_instr ? { {21{$instr[31]}}, $instr[30:25], $instr[11:7] } :
$is_b_instr ? { {20{$instr[31]}}, $instr[7], $instr[30:25], $instr[11:8], 1'b0 } :
$is_u_instr ? { $instr[31], $instr[30:12], 12'b0 } :
$is_j_instr ? { {12{$instr[31]}}, $instr[19:12], $instr[20], $instr[30:21], 1'b0 } :
32'b0;
// Assert these to end simulation (before Makerchip cycle limit). // Assert these to end simulation (before Makerchip cycle limit).
*passed = 1'b0; *passed = 1'b0;
*failed = *cyc_cnt > M4_MAX_CYC; *failed = *cyc_cnt > M4_MAX_CYC;