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LF-Building-a-RISC-V-CPU-Core
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Disable writing to register 0

This commit is contained in:
Victor Timofei 2022-01-11 21:20:03 +02:00
parent 92c9d9c91e
commit a7d3c26f76
Signed by: vtimofei
GPG Key ID: B790DCEBE281403A
1 changed files with 2 additions and 1 deletions
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risc-v_shell.tlv
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@ -73,7 +73,8 @@
$func3_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
$rs2_valid = $is_r_instr || $is_s_instr || $is_b_instr;
$rs1_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
$rd_valid = $is_r_instr || $is_i_instr || $is_u_instr || $is_j_instr;
$rd_valid = $rd == 0 ? 0 :
$is_r_instr || $is_i_instr || $is_u_instr || $is_j_instr;
$imm_valid = $is_i_instr || $is_s_instr || $is_b_instr || $is_u_instr || $is_j_instr;
`BOGUS_USE($rd $rd_valid $rs1 $rs1_valid $rs2 $rs2_valid $func3 $func3_valid $imm_valid $opcode)