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LF-Building-a-RISC-V-CPU-Core
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Add `add` instructions for ALU and disable write

This commit is contained in:
Victor Timofei 2022-01-11 21:04:31 +02:00
parent 432ce28d5d
commit 85eebd8a1b
Signed by: vtimofei
GPG Key ID: B790DCEBE281403A
1 changed files with 8 additions and 0 deletions
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8
risc-v_shell.tlv
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@ -103,7 +103,15 @@
*passed = 1'b0; *passed = 1'b0;
*failed = *cyc_cnt > M4_MAX_CYC; *failed = *cyc_cnt > M4_MAX_CYC;
// Arithmetic Logic Unit
$result[31:0] =
$is_addi ? $src1_value + $imm :
$is_add ? $src1_value + $src2_value :
32'b0;
// Register file // Register file
// TODO: this is for debugging only, REMOVE ME
$rd_valid = 1'b0;
m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $wr_data[31:0], $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value) m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $wr_data[31:0], $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
//m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data) //m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
m4+cpu_viz() m4+cpu_viz()