From 85eebd8a1b309c3c7fcc8ab0497aebe71b371c9c Mon Sep 17 00:00:00 2001
From: Victor Timofei <victor@vtimothy.com>
Date: Tue, 11 Jan 2022 21:04:31 +0200
Subject: [PATCH] Add `add` instructions for ALU and disable write

---
 risc-v_shell.tlv | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/risc-v_shell.tlv b/risc-v_shell.tlv
index 865273e..cea5909 100644
--- a/risc-v_shell.tlv
+++ b/risc-v_shell.tlv
@@ -103,7 +103,15 @@
    *passed = 1'b0;
    *failed = *cyc_cnt > M4_MAX_CYC;
 
+   // Arithmetic Logic Unit
+   $result[31:0] =
+      $is_addi ? $src1_value + $imm :
+      $is_add ? $src1_value + $src2_value :
+      32'b0;
+
    // Register file
+   // TODO: this is for debugging only, REMOVE ME
+   $rd_valid = 1'b0;
    m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $wr_data[31:0], $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
    //m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
    m4+cpu_viz()