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LF-Building-a-RISC-V-CPU-Core
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Decode instruction types

This commit is contained in:
Victor Timofei 2022-01-10 22:04:05 +02:00
parent d5bb6da13c
commit 6c05fd21ef
Signed by: vtimofei
GPG Key ID: B790DCEBE281403A
1 changed files with 14 additions and 4 deletions
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18
risc-v_shell.tlv
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@ -44,14 +44,24 @@
$reset = *reset;
// YOUR CODE HERE
// ...
// Program counter
$next_pc[31:0] = $reset ? 0 : ($pc + 4);
$pc[31:0] = >>1$next_pc;
// Instruction memory
`READONLY_MEM($pc, $$instr[31:0]);
// Decode instruction types
$is_u_instr = $instr[6:2] ==? 5'b0x101;
$is_i_instr = $instr[6:2] ==? 5'b0000x
|| $instr[6:2] ==? 5'b001x0
|| $instr[6:2] == 5'b11001;
$is_r_instr = $instr[6:2] ==? 5'b011x0
|| $instr[6:2] == 5'b01011
|| $instr[6:2] == 5'10100;
$is_s_instr = $instr[6:2] ==? 5'b0100x;
$is_b_instr = $instr[6:2] == 5'b11000;
$is_j_instr = $instr[6:2] == 5'b11011;
// Assert these to end simulation (before Makerchip cycle limit).
*passed = 1'b0;
@ -61,4 +71,4 @@
//m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
m4+cpu_viz()
\SV
endmodule
endmodule