From 6c05fd21ef5bee3993bdbb6dc24f06a0cf942114 Mon Sep 17 00:00:00 2001
From: Victor Timofei <victor@vtimothy.com>
Date: Mon, 10 Jan 2022 22:04:05 +0200
Subject: [PATCH] Decode instruction types

---
 risc-v_shell.tlv | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/risc-v_shell.tlv b/risc-v_shell.tlv
index f037618..fb55cde 100644
--- a/risc-v_shell.tlv
+++ b/risc-v_shell.tlv
@@ -44,14 +44,24 @@
    $reset = *reset;
    
    
-   // YOUR CODE HERE
-   // ...
+   // Program counter
    $next_pc[31:0] = $reset ? 0 : ($pc + 4);
-
    $pc[31:0] = >>1$next_pc;
 
+   // Instruction memory
    `READONLY_MEM($pc, $$instr[31:0]);
    
+   // Decode instruction types
+   $is_u_instr = $instr[6:2] ==? 5'b0x101;
+   $is_i_instr = $instr[6:2] ==? 5'b0000x
+      || $instr[6:2] ==? 5'b001x0
+      || $instr[6:2] == 5'b11001;
+   $is_r_instr = $instr[6:2] ==? 5'b011x0
+      || $instr[6:2] == 5'b01011
+      || $instr[6:2] == 5'10100;
+   $is_s_instr = $instr[6:2] ==? 5'b0100x;
+   $is_b_instr = $instr[6:2] == 5'b11000;
+   $is_j_instr = $instr[6:2] == 5'b11011;
    
    // Assert these to end simulation (before Makerchip cycle limit).
    *passed = 1'b0;
@@ -61,4 +71,4 @@
    //m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
    m4+cpu_viz()
 \SV
-   endmodule
\ No newline at end of file
+   endmodule