45 lines
1.7 KiB
Plaintext
45 lines
1.7 KiB
Plaintext
\m4_TLV_version 1d: tl-x.org
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\SV
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// ==================================================
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// For use in the Building a RISC-V CPU Core Course.
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// Provides reference solutions without visibility to source code.
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// ==================================================
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// ----------------------------------
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// Instructions:
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// - When stuck on a particular lab, select the lab at the bottom of this file,
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// and compile/simulate.
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// - A reference solution will build, but the source code will not be visible.
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// - You may use waveforms, diagrams, and visualization to understand the proper circuit, but you
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// will have to come up with the code. Logic expression syntax can be found by hovering over the
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// signal assignment in the diagram.
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// - Course updates can be found here: https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core
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// ----------------------------------
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// Include solutions.
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m4_include_makerchip_hidden(['LF_workshop_solutions.private.tlv'])
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\SV
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// Macro providing required top-level module definition, random
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// stimulus support, and Verilator config.
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m4_makerchip_module // (Expanded in Nav-TLV pane.)
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\TLV
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//=================\
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// Choose Your Lab |
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//=================/
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// Specify which lab you are on by providing a macro argument...
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m4+solution(START)
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// ...from these:
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// Chapter 4:
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// START, PC, IMEM, INSTR_TYPE, FIELDS, IMM, SUBSET_INSTRS,
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// RF_MACRO, RF_READ, SUBSET_ALU, RF_WRITE, TAKEN_BR, BR_REDIR, TB,
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// Chapter 5:
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// TEST_PROG, ALL_INSTRS, FULL_ALU, JUMP, LD_ST_ADDR, DMEM, LD_DATA, DONE
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\SV
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endmodule
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