vtimofei
/
LF-Building-a-RISC-V-CPU-Core
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
10 Commits 1 Branch 0 Tags 272 KiB
SVG 100%
Go to file
Steve Hoover d3872a0fe1 Refinements to full_riscv.tlv and copied to lib/risc-v_shell_lib.tlv to serve as reference solution and library. 2021-02-09 18:22:48 -05:00
lib Refinements to full_riscv.tlv and copied to lib/risc-v_shell_lib.tlv to serve as reference solution and library. 2021-02-09 18:22:48 -05:00
README.md Update README.md 2021-02-08 14:37:13 -05:00
full_riscv.tlv Refinements to full_riscv.tlv and copied to lib/risc-v_shell_lib.tlv to serve as reference solution and library. 2021-02-09 18:22:48 -05:00
risc-v_shell.tlv Update risc-v_shell.tlv 2021-02-09 19:26:03 +05:30

README.md

Building a RISC-V CPU Core

Accompanying resources for the Building a RISC-V CPU Core EdX course by Steve Hoover of Redwood EDA, Linux Foundation, and RISC-V International.

RISC-V Starting-Point Code

To begin the first RISC-V lab, use this link to open starting-point code in makerchip.

RISC-V Reference Solution

In case you get stuck, use this reference solution to help with syntax, etc.

Final Result:

Final Core