956 lines
40 KiB
Plaintext
956 lines
40 KiB
Plaintext
\m4_TLV_version 1d: tl-x.org
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\SV
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m4_include_lib(['https://raw.githubusercontent.com/stevehoover/warp-v_includes/2d6d36baa4d2bc62321f982f78c8fe1456641a43/risc-v_defs.tlv'])
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// v====================== lib/risc-v_shell_lib.tlv =======================v
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// Configuration for WARP-V definitions.
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m4+definitions(['
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m4_define_vector(['M4_WORD'], 32)
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m4_define(['M4_EXT_I'], 1)
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m4_define(['M4_NUM_INSTRS'], 0)
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m4_echo(m4tlv_riscv_gen__body())
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// A single-line M4 macro instantiated at the end of the asm code.
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// It actually produces a definition of an SV macro that instantiates the IMem conaining the program (that can be parsed without \SV_plus).
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m4_define(['m4_asm_end'], ['`define READONLY_MEM(ADDR, DATA) logic [31:0] instrs [0:M4_NUM_INSTRS-1]; assign DATA \= instrs[ADDR[\$clog2(\$size(instrs)) + 1 : 2]]; assign instrs \= '{m4_instr0['']m4_forloop(['m4_instr_ind'], 1, M4_NUM_INSTRS, [', m4_echo(['m4_instr']m4_instr_ind)'])};'])
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m4_define(['m4_lab'], 0)
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m4_define(['m4_define_labs'], ['
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m4_define(['M4_$1_LAB'], m4_lab)
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m4_define(['m4_lab'], m4_eval(m4_lab + 1))
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m4_ifelse(['$1'], [''], [''], ['m4_define_labs(m4_shift($@))'])
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'])
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m4_define_labs(START, PC, IMEM, INSTR_TYPE, FIELDS, IMM, SUBSET_INSTRS, RF_MACRO, RF_READ, SUBSET_ALU, RF_WRITE, TAKEN_BR, BR_REDIR, TB,
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TEST_PROG, ALL_INSTRS, FULL_ALU, JUMP, LD_ST_ADDR, DMEM, LD_DATA, DONE)
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m4_define(['m4_reached'], ['m4_eval(M4_LAB >= M4_$1_LAB), 1'])
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'])
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// Register File
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\TLV rf(_entries, _width, $_reset, $_port1_en, $_port1_index, $_port1_data, $_port2_en, $_port2_index, $_port2_data, $_port3_en, $_port3_index, $_port3_data)
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$rf1_wr_en = m4_argn(4, $@);
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$rf1_wr_index[\$clog2(_entries)-1:0] = m4_argn(5, $@);
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$rf1_wr_data[_width-1:0] = m4_argn(6, $@);
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$rf1_rd_en1 = m4_argn(7, $@);
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$rf1_rd_index1[\$clog2(_entries)-1:0] = m4_argn(8, $@);
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$rf1_rd_en2 = m4_argn(10, $@);
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$rf1_rd_index2[\$clog2(_entries)-1:0] = m4_argn(11, $@);
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/xreg[m4_eval(_entries-1):0]
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$wr = /top$rf1_wr_en && (/top$rf1_wr_index == #xreg);
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<<1$value[_width-1:0] = /top$_reset ? #xreg :
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$wr ? /top$rf1_wr_data :
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$RETAIN;
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$_port2_data[_width-1:0] = $rf1_rd_en1 ? /xreg[$rf1_rd_index1]$value : 'X;
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$_port3_data[_width-1:0] = $rf1_rd_en2 ? /xreg[$rf1_rd_index2]$value : 'X;
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/xreg[m4_eval(_entries-1):0]
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\viz_alpha
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initEach: function() {
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return {} // {objects: {reg: reg}};
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},
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renderEach: function() {
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siggen = (name) => this.svSigRef(`${name}`) == null ? this.svSigRef(`sticky_zero`) : this.svSigRef(`${name}`);
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let rf_rd_en1 = siggen(`L0_rf1_rd_en1_a0`)
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let rf_rd_index1 = siggen(`L0_rf1_rd_index1_a0`)
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let rf_rd_en2 = siggen(`L0_rf1_rd_en2_a0`)
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let rf_rd_index2 = siggen(`L0_rf1_rd_index2_a0`)
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let rf_wr_index = siggen(`rf1_wr_index_a0`)
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let wr = siggen(`L1_Xreg[${this.getIndex()}].L1_wr_a0`)
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let value = siggen(`Xreg_value_a0(${this.getIndex()})`)
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let rd = (rf_rd_en1.asBool(false) && rf_rd_index1.asInt() == this.getIndex()) ||
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(rf_rd_en2.asBool(false) && rf_rd_index2.asInt() == this.getIndex())
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let mod = wr.asBool(false);
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let reg = parseInt(this.getIndex())
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let regIdent = reg.toString().padEnd(2, " ")
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let newValStr = (regIdent + ": ").padEnd(14, " ")
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let reg_str = new fabric.Text((regIdent + ": " + value.asInt(NaN).toString(M4_VIZ_BASE)).padEnd(14, " "), {
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top: 18 * this.getIndex() - 40,
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left: 316,
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fontSize: 14,
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fill: mod ? "blue" : "black",
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fontWeight: mod ? 800 : 400,
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fontFamily: "monospace",
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textBackgroundColor: rd ? "#b0ffff" : mod ? "#f0f0f0" : "white"
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})
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if (mod) {
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setTimeout(() => {
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reg_str.set({text: newValStr, textBackgroundColor: "#d0e8ff", dirty: true})
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this.global.canvas.renderAll()
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}, 1500)
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}
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return {objects: [reg_str]}
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}
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// Data Memory
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\TLV dmem(_entries, _width, $_reset, $_port1_en, $_port1_index, $_port1_data, $_port2_en, $_port2_index, $_port2_data)
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// Allow expressions for most inputs, so define input signals.
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$dmem1_wr_en = m4_argn(4, $@);
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$dmem1_wr_index[\$clog2(_entries)-1:0] = m4_argn(5, $@);
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$dmem1_wr_data[_width-1:0] = m4_argn(6, $@);
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$dmem1_rd_en = m4_argn(7, $@);
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$dmem1_rd_index[\$clog2(_entries)-1:0] = m4_argn(8, $@);
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/dmem[m4_eval(_entries-1):0]
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$wr = /top$dmem1_wr_en && (/top$dmem1_wr_index == #dmem);
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<<1$value[_width-1:0] = /top$_reset ? 0 :
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$wr ? /top$dmem1_wr_data :
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$RETAIN;
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$_port2_data[_width-1:0] = $dmem1_rd_en ? /dmem[$dmem1_rd_index]$value : 'X;
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/dmem[m4_eval(_entries-1):0]
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\viz_alpha
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initEach: function() {
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return {} // {objects: {reg: reg}};
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},
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renderEach: function() {
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siggen = (name) => this.svSigRef(`${name}`) == null ? this.svSigRef(`sticky_zero`) : this.svSigRef(`${name}`);
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//
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let dmem_rd_en = siggen(`L0_dmem1_rd_en_a0`);
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let dmem_rd_index = siggen(`L0_dmem1_rd_index_a0`);
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let dmem_wr_index = siggen(`L0_dmem1_wr_index_a0`);
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//
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let wr = siggen(`L1_Dmem[${this.getIndex()}].L1_wr_a0`);
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let value = siggen(`Dmem_value_a0(${this.getIndex()})`);
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//
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let rd = dmem_rd_en.asBool() && dmem_rd_index.asInt() == this.getIndex();
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let mod = wr.asBool(false);
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let reg = parseInt(this.getIndex());
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let regIdent = reg.toString().padEnd(2, " ");
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let newValStr = (regIdent + ": ").padEnd(14, " ");
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let dmem_str = new fabric.Text((regIdent + ": " + value.asInt(NaN).toString(M4_VIZ_BASE)).padEnd(14, " "), {
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top: 18 * this.getIndex() - 40,
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left: 480,
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fontSize: 14,
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fill: mod ? "blue" : "black",
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fontWeight: mod ? 800 : 400,
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fontFamily: "monospace",
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textBackgroundColor: rd ? "#b0ffff" : mod ? "#d0e8ff" : "white"
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})
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if (mod) {
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setTimeout(() => {
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dmem_str.set({text: newValStr, dirty: true})
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this.global.canvas.renderAll()
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}, 1500)
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}
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return {objects: [dmem_str]}
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}
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\TLV cpu_viz()
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// String representations of the instructions for debug.
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\SV_plus
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// A default signal for ones that are not found.
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logic sticky_zero;
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assign sticky_zero = 0;
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// Instruction strings from the assembler.
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logic [40*8-1:0] instr_strs [0:M4_NUM_INSTRS];
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assign instr_strs = '{m4_asm_mem_expr "END "};
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/cpuviz
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\viz_alpha
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m4_define(['M4_IMEM_TOP'], ['m4_ifelse(m4_eval(M4_NUM_INSTRS > 16), 0, 0, m4_eval(0 - (M4_NUM_INSTRS - 16) * 18))'])
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initEach() {
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let imem_box = new fabric.Rect({
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top: M4_IMEM_TOP - 50,
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left: -700,
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fill: "#208028",
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width: 665,
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height: 76 + 18 * M4_NUM_INSTRS,
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stroke: "black",
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visible: false
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})
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let decode_box = new fabric.Rect({
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top: -25,
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left: -15,
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fill: "#f8f0e8",
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width: 280,
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height: 215,
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stroke: "#ff8060",
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visible: false
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})
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let rf_box = new fabric.Rect({
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top: -90,
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left: 306,
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fill: "#2028b0",
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width: 145,
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height: 650,
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stroke: "black",
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visible: false
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})
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let dmem_box = new fabric.Rect({
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top: -90,
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left: 470,
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fill: "#208028",
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width: 145,
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height: 650,
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stroke: "black",
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visible: false
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})
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let imem_header = new fabric.Text("🗃️ IMem", {
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top: M4_IMEM_TOP - 35,
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left: -460,
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fontSize: 18,
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fontWeight: 800,
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fontFamily: "monospace",
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fill: "white",
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visible: false
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})
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let decode_header = new fabric.Text("⚙️ Instr. Decode", {
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top: -4,
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left: 20,
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fill: "maroon",
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fontSize: 18,
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fontWeight: 800,
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fontFamily: "monospace",
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visible: false
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})
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let rf_header = new fabric.Text("📂 RF", {
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top: -75,
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left: 316,
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fontSize: 18,
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fontWeight: 800,
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fontFamily: "monospace",
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fill: "white",
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visible: false
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})
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let dmem_header = new fabric.Text("🗃️ DMem", {
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top: -75,
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left: 480,
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fontSize: 18,
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fontWeight: 800,
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fontFamily: "monospace",
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fill: "white",
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visible: false
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})
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let passed = new fabric.Text("", {
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top: 300,
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left: -30,
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fontSize: 46,
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fontWeight: 800
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})
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let missing_col1 = new fabric.Text("", {
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top: 420,
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left: -480,
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fontSize: 16,
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fontWeight: 500,
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fontFamily: "monospace",
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fill: "purple"
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})
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let missing_col2 = new fabric.Text("", {
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top: 420,
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left: -300,
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fontSize: 16,
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fontWeight: 500,
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fontFamily: "monospace",
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fill: "purple"
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})
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let missing_sigs = new fabric.Group(
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[new fabric.Text("🚨 To Be Implemented:", {
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top: 350,
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left: -466,
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fontSize: 18,
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fontWeight: 800,
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fill: "red",
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fontFamily: "monospace"
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}),
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new fabric.Rect({
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top: 400,
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left: -500,
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fill: "#ffffe0",
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width: 400,
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height: 300,
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stroke: "black"
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}),
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missing_col1,
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missing_col2,
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],
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{visible: false}
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)
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return {missing_col1, missing_col2,
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objects: {imem_box, decode_box, rf_box, dmem_box, imem_header, decode_header, rf_header, dmem_header, passed, missing_sigs}};
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},
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renderEach() {
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// Strings (2 columns) of missing signals.
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var missing_list = ["", ""]
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var missing_cnt = 0
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let sticky_zero = this.svSigRef(`sticky_zero`); // A default zero-valued signal.
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// Attempt to look up a signal, using sticky_zero as default and updating missing_list if expected.
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siggen = (name, full_name, expected = true) => {
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var sig = this.svSigRef(full_name ? full_name : `L0_${name}_a0`)
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if (sig == null) {
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sig = sticky_zero;
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if (expected) {
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missing_list[missing_cnt > 11 ? 1 : 0] += `◾ $${name} \n`;
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missing_cnt++
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}
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}
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return sig
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}
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// Look up signal, and it's ok if it doesn't exist.
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siggen_rf_dmem = (name, scope) => {
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return siggen(name, scope, false)
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}
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// Determine which is_xxx signal is asserted.
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siggen_mnemonic = () => {
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let instrs = ["lui", "auipc", "jal", "jalr", "beq", "bne", "blt", "bge", "bltu", "bgeu", "lb", "lh", "lw", "lbu", "lhu", "sb", "sh", "sw", "addi", "slti", "sltiu", "xori", "ori", "andi", "slli", "srli", "srai", "add", "sub", "sll", "slt", "sltu", "xor", "srl", "sra", "or", "and", "csrrw", "csrrs", "csrrc", "csrrwi", "csrrsi", "csrrci", "load", "s_instr"];
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for(i=0;i<instrs.length;i++) {
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var sig = this.svSigRef(`L0_is_${instrs[i]}_a0`)
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if(sig != null && sig.asBool()) {
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return instrs[i].toUpperCase()
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}
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}
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return "ILLEGAL"
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}
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let pc = siggen("pc")
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let instr = siggen("instr")
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let types = {I: siggen("is_i_instr"),
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R: siggen("is_r_instr"),
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S: siggen("is_s_instr"),
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B: siggen("is_b_instr"),
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J: siggen("is_j_instr"),
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U: siggen("is_u_instr"),
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}
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let rd_valid = siggen("rd_valid")
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let rd = siggen("rd")
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let result = siggen("result")
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let src1_value = siggen("src1_value")
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let src2_value = siggen("src2_value")
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let imm = siggen("imm")
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let imm_valid = siggen("imm_valid")
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let rs1 = siggen("rs1")
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let rs2 = siggen("rs2")
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let rs1_valid = siggen("rs1_valid")
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let rs2_valid = siggen("rs2_valid")
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let ld_data = siggen("ld_data")
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let mnemonic = siggen_mnemonic()
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let dummy = siggen("dummy")
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let passed = siggen("passed_cond", false, false)
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let rf_rd_en1 = siggen_rf_dmem("rf1_rd_en1")
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let rf_rd_index1 = siggen_rf_dmem("rf1_rd_index1")
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let rf_rd_en2 = siggen_rf_dmem("rf1_rd_en2")
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let rf_rd_index2 = siggen_rf_dmem("rf1_rd_index2")
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let rf_wr_en = siggen_rf_dmem("rf1_wr_en")
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let rf_wr_index = siggen_rf_dmem("rf1_wr_index")
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let rf_wr_data = siggen_rf_dmem("rf1_wr_data")
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let dmem_rd_en = siggen_rf_dmem("dmem1_rd_en")
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let dmem_rd_index = siggen_rf_dmem("dmem1_rd_index")
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let dmem_wr_en = siggen_rf_dmem("dmem1_wr_en")
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let dmem_wr_index = siggen_rf_dmem("dmem1_wr_index")
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if (instr != sticky_zero) {
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this.getInitObjects().imem_box.setVisible(true)
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this.getInitObjects().imem_header.setVisible(true)
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this.getInitObjects().decode_box.setVisible(true)
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this.getInitObjects().decode_header.setVisible(true)
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}
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let pcPointer = new fabric.Text("👉", {
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top: M4_IMEM_TOP + 18 * (pc.asInt() / 4),
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left: -375,
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fill: "blue",
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fontSize: 14,
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fontFamily: "monospace",
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visible: pc != sticky_zero
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})
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let pc_arrow = new fabric.Line([-57, M4_IMEM_TOP + 18 * (pc.asInt() / 4) + 6, 6, 35], {
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stroke: "#b0c8df",
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strokeWidth: 2,
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visible: instr != sticky_zero
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})
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// Display instruction type(s)
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let type_texts = []
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for (const [type, sig] of Object.entries(types)) {
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if (sig.asBool()) {
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type_texts.push(
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new fabric.Text(`(${type})`, {
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top: 60,
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left: 10,
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fill: "blue",
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fontSize: 20,
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fontFamily: "monospace"
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})
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)
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}
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}
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let rs1_arrow = new fabric.Line([330, 18 * rf_rd_index1.asInt() + 6 - 40, 190, 75 + 18 * 2], {
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stroke: "#b0c8df",
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strokeWidth: 2,
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visible: rf_rd_en1.asBool()
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})
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let rs2_arrow = new fabric.Line([330, 18 * rf_rd_index2.asInt() + 6 - 40, 190, 75 + 18 * 3], {
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stroke: "#b0c8df",
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strokeWidth: 2,
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visible: rf_rd_en2.asBool()
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})
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let rd_arrow = new fabric.Line([330, 18 * rf_wr_index.asInt() + 6 - 40, 168, 75 + 18 * 0], {
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stroke: "#b0b0df",
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strokeWidth: 3,
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visible: rf_wr_en.asBool()
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})
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let ld_arrow = new fabric.Line([490, 18 * dmem_rd_index.asInt() + 6 - 40, 168, 75 + 18 * 0], {
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stroke: "#b0c8df",
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strokeWidth: 2,
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visible: dmem_rd_en.asBool()
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})
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let st_arrow = new fabric.Line([490, 18 * dmem_wr_index.asInt() + 6 - 40, 190, 75 + 18 * 3], {
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stroke: "#b0b0df",
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strokeWidth: 3,
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visible: dmem_wr_en.asBool()
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})
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if (rf_rd_en1 != sticky_zero) {
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this.getInitObjects().rf_box.setVisible(true)
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|
this.getInitObjects().rf_header.setVisible(true)
|
|
}
|
|
if (dmem_rd_en != sticky_zero) {
|
|
this.getInitObjects().dmem_box.setVisible(true)
|
|
this.getInitObjects().dmem_header.setVisible(true)
|
|
}
|
|
|
|
|
|
// Instruction with values
|
|
|
|
let regStr = (valid, regNum, regValue) => {
|
|
return valid ? `r${regNum}` : `rX` // valid ? `r${regNum} (${regValue})` : `rX`
|
|
}
|
|
let immStr = (valid, immValue) => {
|
|
immValue = parseInt(immValue,2) + 2*(immValue[0] << 31)
|
|
return valid ? `i[${immValue}]` : ``;
|
|
}
|
|
let srcStr = ($src, $valid, $reg, $value) => {
|
|
return $valid.asBool(false)
|
|
? `\n ${regStr(true, $reg.asInt(NaN), $value.asInt(NaN))}`
|
|
: "";
|
|
}
|
|
let str = `${regStr(rd_valid.asBool(false), rd.asInt(NaN), result.asInt(NaN))}\n` +
|
|
` = ${mnemonic}${srcStr(1, rs1_valid, rs1, src1_value)}${srcStr(2, rs2_valid, rs2, src2_value)}\n` +
|
|
` ${immStr(imm_valid.asBool(false), imm.asBinaryStr("0"))}`;
|
|
let instrWithValues = new fabric.Text(str, {
|
|
top: 70,
|
|
left: 65,
|
|
fill: "blue",
|
|
fontSize: 14,
|
|
fontFamily: "monospace",
|
|
visible: instr != sticky_zero
|
|
})
|
|
|
|
|
|
// Animate fetch (and provide onChange behavior for other animation).
|
|
|
|
let fetch_instr_str = siggen(`instr_strs(${pc.asInt() >> 2})`, `instr_strs(${pc.asInt() >> 2})`).asString("(?) UNKNOWN fetch instr").substr(4)
|
|
let fetch_instr_viz = new fabric.Text(fetch_instr_str, {
|
|
top: M4_IMEM_TOP + 18 * (pc.asInt() >> 2),
|
|
left: -352 + 8 * 4,
|
|
fill: "black",
|
|
fontSize: 14,
|
|
fontFamily: "monospace",
|
|
visible: instr != sticky_zero
|
|
})
|
|
fetch_instr_viz.animate({top: 32, left: 10}, {
|
|
onChange: this.global.canvas.renderAll.bind(this.global.canvas),
|
|
duration: 500
|
|
})
|
|
|
|
// Animate RF value read/write.
|
|
|
|
let src1_value_viz = new fabric.Text(src1_value.asInt(0).toString(M4_VIZ_BASE), {
|
|
left: 316 + 8 * 4,
|
|
top: 18 * rs1.asInt(0) - 40,
|
|
fill: "blue",
|
|
fontSize: 14,
|
|
fontFamily: "monospace",
|
|
fontWeight: 800,
|
|
visible: (src1_value != sticky_zero) && rs1_valid.asBool(false)
|
|
})
|
|
setTimeout(() => {src1_value_viz.animate({left: 166, top: 70 + 18 * 2}, {
|
|
onChange: this.global.canvas.renderAll.bind(this.global.canvas),
|
|
duration: 500
|
|
})}, 500)
|
|
let src2_value_viz = new fabric.Text(src2_value.asInt(0).toString(M4_VIZ_BASE), {
|
|
left: 316 + 8 * 4,
|
|
top: 18 * rs2.asInt(0) - 40,
|
|
fill: "blue",
|
|
fontSize: 14,
|
|
fontFamily: "monospace",
|
|
fontWeight: 800,
|
|
visible: (src2_value != sticky_zero) && rs2_valid.asBool(false)
|
|
})
|
|
setTimeout(() => {src2_value_viz.animate({left: 166, top: 70 + 18 * 3}, {
|
|
onChange: this.global.canvas.renderAll.bind(this.global.canvas),
|
|
duration: 500
|
|
})}, 500)
|
|
|
|
let load_viz = new fabric.Text(ld_data.asInt(0).toString(M4_VIZ_BASE), {
|
|
left: 470,
|
|
top: 18 * dmem_rd_index.asInt() + 6 - 40,
|
|
fill: "blue",
|
|
fontSize: 14,
|
|
fontFamily: "monospace",
|
|
fontWeight: 1000,
|
|
visible: false
|
|
})
|
|
if (dmem_rd_en.asBool()) {
|
|
setTimeout(() => {
|
|
load_viz.setVisible(true)
|
|
load_viz.animate({left: 146, top: 70}, {
|
|
onChange: this.global.canvas.renderAll.bind(this.global.canvas),
|
|
duration: 500
|
|
})
|
|
setTimeout(() => {
|
|
load_viz.setVisible(false)
|
|
}, 500)
|
|
}, 500)
|
|
}
|
|
|
|
let store_viz = new fabric.Text(src2_value.asInt(0).toString(M4_VIZ_BASE), {
|
|
left: 166,
|
|
top: 70 + 18 * 3,
|
|
fill: "blue",
|
|
fontSize: 14,
|
|
fontFamily: "monospace",
|
|
fontWeight: 1000,
|
|
visible: false
|
|
})
|
|
if (dmem_wr_en.asBool()) {
|
|
setTimeout(() => {
|
|
store_viz.setVisible(true)
|
|
store_viz.animate({left: 515, top: 18 * dmem_wr_index.asInt() - 40}, {
|
|
onChange: this.global.canvas.renderAll.bind(this.global.canvas),
|
|
duration: 500
|
|
})
|
|
}, 1000)
|
|
}
|
|
|
|
let result_shadow = new fabric.Text(result.asInt(0).toString(M4_VIZ_BASE), {
|
|
left: 146,
|
|
top: 70,
|
|
fill: "#b0b0df",
|
|
fontSize: 14,
|
|
fontFamily: "monospace",
|
|
fontWeight: 800,
|
|
visible: false
|
|
})
|
|
let result_viz = new fabric.Text(rf_wr_data.asInt(0).toString(M4_VIZ_BASE), {
|
|
left: 146,
|
|
top: 70,
|
|
fill: "blue",
|
|
fontSize: 14,
|
|
fontFamily: "monospace",
|
|
fontWeight: 800,
|
|
visible: false
|
|
})
|
|
if (rd_valid.asBool()) {
|
|
setTimeout(() => {
|
|
result_viz.setVisible(rf_wr_data != sticky_zero && rf_wr_en.asBool())
|
|
result_shadow.setVisible(result != sticky_zero)
|
|
result_viz.animate({left: 317 + 8 * 4, top: 18 * rf_wr_index.asInt(0) - 40}, {
|
|
onChange: this.global.canvas.renderAll.bind(this.global.canvas),
|
|
duration: 500
|
|
})
|
|
}, 1000)
|
|
}
|
|
|
|
// Lab completion
|
|
|
|
// Passed?
|
|
this.getInitObject("passed").setVisible(false)
|
|
if (passed) {
|
|
if (passed.step(-1).asBool()) {
|
|
this.getInitObject("passed").set({visible: true, text:"Passed !!!", fill: "green"})
|
|
} else {
|
|
// Using an unstable API, so:
|
|
try {
|
|
passed.goTo(passed.sikkkgnal.waveData.endCycle - 1)
|
|
if (passed.asBool()) {
|
|
this.getInitObject("passed").set({text:"Sim Passes", visible: true, fill: "lightgray"})
|
|
}
|
|
} catch(e) {
|
|
}
|
|
}
|
|
}
|
|
|
|
// Missing signals
|
|
if (missing_list[0]) {
|
|
this.getInitObject("missing_sigs").setVisible(true)
|
|
this.fromInit().missing_col1.setText(missing_list[0])
|
|
this.fromInit().missing_col2.setText(missing_list[1])
|
|
}
|
|
return {objects: [pcPointer, pc_arrow, ...type_texts, rs1_arrow, rs2_arrow, rd_arrow, instrWithValues, fetch_instr_viz, src1_value_viz, src2_value_viz, result_shadow, result_viz, ld_arrow, st_arrow, load_viz, store_viz]};
|
|
}
|
|
|
|
/imem[m4_eval(M4_NUM_INSTRS-1):0]
|
|
\viz_alpha
|
|
initEach() {
|
|
let binary = new fabric.Text("", {
|
|
top: M4_IMEM_TOP + 18 * this.getIndex(),
|
|
left: -680,
|
|
fontSize: 14,
|
|
fontFamily: "monospace",
|
|
|
|
})
|
|
let disassembled = new fabric.Text("", {
|
|
top: M4_IMEM_TOP + 18 * this.getIndex(),
|
|
left: -350,
|
|
fontSize: 14,
|
|
fontFamily: "monospace"
|
|
})
|
|
return {objects: {binary, disassembled}}
|
|
},
|
|
renderEach() {
|
|
// Instruction memory is constant, so just create it once.
|
|
let reset = this.svSigRef(`L0_reset_a0`)
|
|
let pc = this.svSigRef(`L0_pc_a0`)
|
|
let rd_viz = pc && !reset.asBool() && (pc.asInt() >> 2) == this.getIndex()
|
|
if (!global.instr_mem_drawn) {
|
|
global.instr_mem_drawn = []
|
|
}
|
|
if (!global.instr_mem_drawn[this.getIndex()]) {
|
|
global.instr_mem_drawn[this.getIndex()] = true
|
|
|
|
let instr = this.svSigRef(`instrs(${this.getIndex()})`)
|
|
if (instr) {
|
|
let binary_str = instr.asBinaryStr("")
|
|
this.getInitObject("binary").setText(binary_str)
|
|
}
|
|
let disassembled = this.svSigRef(`instr_strs(${this.getIndex()})`)
|
|
if (disassembled) {
|
|
let disassembled_str = disassembled.asString("")
|
|
disassembled_str = disassembled_str.slice(0, -5)
|
|
this.getInitObject("disassembled").setText(disassembled_str)
|
|
}
|
|
}
|
|
this.getInitObject("disassembled").set({textBackgroundColor: rd_viz ? "#b0ffff" : "white"})
|
|
this.getInitObject("binary") .set({textBackgroundColor: rd_viz ? "#b0ffff" : "white"})
|
|
}
|
|
|
|
\TLV tb()
|
|
$passed_cond = (/xreg[30]$value == 32'b1) &&
|
|
(! $reset && $next_pc[31:0] == $pc[31:0]);
|
|
*passed = >>2$passed_cond;
|
|
|
|
\TLV test_prog()
|
|
// /=======================\
|
|
// | Test each instruction |
|
|
// \=======================/
|
|
//
|
|
// Some constant values to use as operands.
|
|
m4_asm(ADDI, r1, r0, 10101) // An operand value of 21.
|
|
m4_asm(ADDI, r2, r0, 111) // An operand value of 7.
|
|
m4_asm(XORI, r3, r0, 111111111100) // An operand value of -4.
|
|
// Execute one of each instruction, XORing subtracting (via ADDI) the expected value.
|
|
m4_asm(ANDI, r5, r1, 1011100)
|
|
m4_asm(XORI, r5, r5, 10100)
|
|
m4_asm(ORI, r6, r1, 1011100)
|
|
m4_asm(XORI, r6, r6, 1011101)
|
|
m4_asm(ADDI, r7, r1, 111)
|
|
m4_asm(XORI, r7, r7, 11100)
|
|
m4_asm(SLLI, r8, r1, 110)
|
|
m4_asm(XORI, r8, r8, 10101000000)
|
|
m4_asm(SRLI, r9, r1, 10)
|
|
m4_asm(XORI, r9, r9, 101)
|
|
m4_asm(AND, r10, r1, r2)
|
|
m4_asm(XORI, r10, r10, 101)
|
|
m4_asm(OR, r11, r1, r2)
|
|
m4_asm(XORI, r11, r11, 10111)
|
|
m4_asm(XOR, r12, r1, r2)
|
|
m4_asm(XORI, r12, r12, 10010)
|
|
m4_asm(ADD, r13, r1, r2)
|
|
m4_asm(XORI, r13, r13, 11100)
|
|
m4_asm(SUB, r14, r1, r2)
|
|
m4_asm(XORI, r14, r14, 1110)
|
|
m4_asm(SLL, r15, r2, r2)
|
|
m4_asm(XORI, r15, r15, 1110000000)
|
|
m4_asm(SRL, r16, r1, r2)
|
|
m4_asm(XORI, r16, r16, 0)
|
|
m4_asm(SLTU, r17, r2, r1)
|
|
m4_asm(XORI, r17, r17, 1)
|
|
m4_asm(SLTIU, r18, r2, 10101)
|
|
m4_asm(XORI, r18, r18, 1)
|
|
m4_asm(LUI, r19, 0)
|
|
m4_asm(XORI, r19, r19, 0)
|
|
m4_asm(SRAI, r20, r3, 1)
|
|
m4_asm(XORI, r20, r20, 111111111110)
|
|
m4_asm(SLT, r21, r3, r1)
|
|
m4_asm(XORI, r21, r21, 1)
|
|
m4_asm(SLTI, r22, r3, 1)
|
|
m4_asm(XORI, r22, r22, 1)
|
|
m4_asm(SRA, r23, r1, r2)
|
|
m4_asm(XORI, r23, r23, 0)
|
|
// Test AUIPC. PC is >= 32 and < 64 instructions. JAL, and JALR together. Their PCs should differ by 4.
|
|
m4_asm(AUIPC, r4, 100)
|
|
m4_asm(SRLI, r24, r4, 111)
|
|
m4_asm(XORI, r24, r24, 10000001)
|
|
m4_asm(JAL, r25, 10) // r25 = PC of next instr
|
|
m4_asm(AUIPC, r4, 0) // r4 = PC
|
|
m4_asm(XOR, r25, r25, r4) # AUIPC and JAR results are the same.
|
|
m4_asm(JALR, r26, r4, 1100)
|
|
m4_asm(SUB, r26, r26, r4) // JALR PC+4 - AUIPC PC
|
|
m4_asm(XORI, r26, r26, 1100) // - 4 instrs
|
|
//m4_asm(SW, r27,
|
|
m4_asm(SW, r2, r1, 1)
|
|
m4_asm(LW, r27, r2, 1)
|
|
m4_asm(XOR, r27, r27, r1)
|
|
// Set r30[0], so always report passed on completion, regardless of registers containing zeros.
|
|
m4_asm(ADDI, r30, r0, 1)
|
|
m4_asm(JAL, r0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
|
|
m4_asm_end()
|
|
m4_define(['M4_MAX_CYC'], 50)
|
|
|
|
\TLV sum_prog()
|
|
// /====================\
|
|
// | Sum 1 to 9 Program |
|
|
// \====================/
|
|
//
|
|
// Program to test RV32I
|
|
// Add 1,2,3,...,9 (in that order).
|
|
//
|
|
// Regs:
|
|
// r12 (a2): 10
|
|
// r13 (a3): 1..10
|
|
// r14 (a4): Sum
|
|
//
|
|
m4_asm(ADDI, r14, r0, 0) // Initialize sum register a4 with 0
|
|
m4_asm(ADDI, r12, r0, 1010) // Store count of 10 in register a2.
|
|
m4_asm(ADDI, r13, r0, 1) // Initialize loop count register a3 with 0
|
|
// Loop:
|
|
m4_asm(ADD, r14, r13, r14) // Incremental summation
|
|
m4_asm(ADDI, r13, r13, 1) // Increment loop count by 1
|
|
m4_asm(BLT, r13, r12, 1111111111000) // If a3 is less than a2, branch to label named <loop>
|
|
// Test result value in r14, and set r31 to reflect pass/fail.
|
|
m4_asm(ADDI, r30, r14, 111111010100) // Subtract expected value of 44 to set r30 to 1 if and only iff the result is 45 (1 + 2 + ... + 9).
|
|
m4_asm(BGE, r0, r0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
|
|
m4_asm_end()
|
|
m4_define(['M4_MAX_CYC'], 50)
|
|
|
|
|
|
// ^===================================================================^
|
|
|
|
\SV
|
|
m4_makerchip_module // (Expanded in Nav-TLV pane.)
|
|
\TLV
|
|
// @@@@@@@@@@@@@@@@@@@@@@@@@@@@@
|
|
// Possible choices for M4_LAB.
|
|
// START, PC, IMEM, INSTR_TYPE, FIELDS, IMM, SUBSET_INSTRS, RF_MACRO, RF_READ, SUBSET_ALU, RF_WRITE, TAKEN_BR, BR_REDIR, TB,
|
|
// TEST_PROG, ALL_INSTRS, FULL_ALU, JUMP, LD_ST_ADDR, DMEM, LD_DATA, DONE
|
|
m4_default(['M4_LAB'], M4_START_LAB)
|
|
// @@@@@@@@@@@@@@@@@@@@@@@@@@@@@
|
|
/* Built for LAB: M4_LAB */
|
|
|
|
m4_ifelse(m4_reached(['TEST_PROG']), ['m4_define(['M4_VIZ_BASE'], 16)']) // (Note that immediate values are shown in disassembled instructions in binary and signed decimal in decoder regardless of this setting.)
|
|
m4_define(['m4_prog_macro'], m4_ifelse(m4_reached(['TEST_PROG']), ['test_prog'], ['sum_prog']))
|
|
m4+m4_prog_macro()
|
|
|
|
//--------------------------------------
|
|
|
|
m4_ifelse_block(m4_reached(['PC']), ['
|
|
$reset = *reset;
|
|
$next_pc[31:0] = $reset ? '0 :
|
|
m4_ifelse_block(m4_reached(['BR_REDIR']), ['
|
|
$taken_br ? $br_tgt_pc :
|
|
'])
|
|
m4_ifelse_block(m4_reached(['JUMP']), ['
|
|
$is_jal ? $br_tgt_pc :
|
|
$is_jalr ? $jalr_tgt_pc :
|
|
'])
|
|
$pc + 32'd4 ;
|
|
$pc[31:0] = >>1$next_pc;
|
|
'])
|
|
|
|
m4_ifelse_block(m4_reached(['IMEM']), ['
|
|
`READONLY_MEM($pc, $$instr[31:0])
|
|
'])
|
|
|
|
m4_ifelse_block(m4_reached(['INSTR_TYPE']), ['
|
|
$is_i_instr = $instr[6:2] ==? 5'b0000x ||
|
|
$instr[6:2] ==? 5'b001x0 ||
|
|
$instr[6:2] ==? 5'b11001 ;
|
|
|
|
$is_r_instr = $instr[6:2] ==? 5'b01011 ||
|
|
$instr[6:2] ==? 5'b011x0 ||
|
|
$instr[6:2] ==? 5'b10100 ;
|
|
|
|
$is_s_instr = $instr[6:2] ==? 5'b0100x;
|
|
|
|
$is_b_instr = $instr[6:2] ==? 5'b11000;
|
|
|
|
$is_j_instr = $instr[6:2] ==? 5'b11011;
|
|
|
|
$is_u_instr = $instr[6:2] ==? 5'b0x101;
|
|
'])
|
|
|
|
m4_ifelse_block(m4_reached(['FIELDS']), ['
|
|
$funct7[6:0] = $instr[31:25];
|
|
$funct3[2:0] = $instr[14:12];
|
|
$rs1[4:0] = $instr[19:15];
|
|
$rs2[4:0] = $instr[24:20];
|
|
$rd[4:0] = $instr[11:7];
|
|
$opcode[6:0] = $instr[6:0];
|
|
|
|
$funct7_valid = $is_r_instr;
|
|
$funct3_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
|
|
$rs1_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr;
|
|
$rs2_valid = $is_r_instr || $is_s_instr || $is_b_instr ;
|
|
$rd_valid = $is_r_instr || $is_i_instr || $is_u_instr || $is_j_instr;
|
|
$imm_valid = $is_i_instr || $is_s_instr || $is_b_instr || $is_u_instr || $is_j_instr;
|
|
'])
|
|
|
|
m4_ifelse_block(m4_reached(['IMM']), ['
|
|
$imm[31:0] = $is_i_instr ? {{21{$instr[31]}}, $instr[30:20]} :
|
|
$is_s_instr ? {{21{$instr[31]}}, $instr[30:25], $instr[11:7]} :
|
|
$is_b_instr ? {{20{$instr[31]}}, $instr[7], $instr[30:25], $instr[11:8], 1'b0} :
|
|
$is_u_instr ? {$instr[31:12], 12'b0} :
|
|
$is_j_instr ? {{12{$instr[31]}}, $instr[19:12], $instr[20], $instr[30:21], 1'b0} :
|
|
32'b0 ;
|
|
'])
|
|
|
|
m4_ifelse_block(m4_reached(['SUBSET_INSTRS']), ['
|
|
$dec_bits[10:0] = {$funct7[5], $funct3, $opcode};
|
|
$is_beq = $dec_bits ==? 11'bx_000_1100011;
|
|
$is_bne = $dec_bits ==? 11'bx_001_1100011;
|
|
$is_blt = $dec_bits ==? 11'bx_100_1100011;
|
|
$is_bge = $dec_bits ==? 11'bx_101_1100011;
|
|
$is_bltu = $dec_bits ==? 11'bx_110_1100011;
|
|
$is_bgeu = $dec_bits ==? 11'bx_111_1100011;
|
|
|
|
$is_addi = $dec_bits ==? 11'bx_000_0010011;
|
|
$is_add = $dec_bits ==? 11'b0_000_0110011;
|
|
'])
|
|
|
|
m4_ifelse_block(m4_reached(['RF_WRITE']), ['
|
|
m4_define(['m4_rf_wr_en'], ['$rd_valid'])
|
|
m4_define(['m4_rf_wr_index'], ['$rd'])
|
|
m4_define(['m4_rf_wr_data'], ['$result'])
|
|
'], ['
|
|
m4_define(['m4_rf_wr_en'], ['$rf_wr_en'])
|
|
m4_define(['m4_rf_wr_index'], ['$rf_wr_index'])
|
|
m4_define(['m4_rf_wr_data'], ['$rf_wr_data'])
|
|
'])
|
|
m4_ifelse_block(m4_reached(['FULL_ALU']), ['
|
|
$sltu_rslt = $src1_value < $src2_value;
|
|
$sltiu_rslt = $src1_value < $imm;
|
|
'])
|
|
m4_ifelse_block(m4_reached(['SUBSET_ALU']), ['
|
|
$result[31:0] = $is_addi ? $src1_value + $imm :
|
|
$is_add ? $src1_value + $src2_value :
|
|
m4_ifelse_block(m4_reached(['FULL_ALU']), ['
|
|
$is_andi ? $src1_value & $imm :
|
|
$is_ori ? $src1_value | $imm :
|
|
$is_xori ? $src1_value ^ $imm :
|
|
$is_slli ? $src1_value << $imm[5:0] :
|
|
$is_srli ? $src1_value >> $imm[5:0] :
|
|
$is_and ? $src1_value & $src2_value :
|
|
$is_or ? $src1_value | $src2_value :
|
|
$is_xor ? $src1_value ^ $src2_value :
|
|
$is_sub ? $src1_value - $src2_value :
|
|
$is_sll ? $src1_value << $src2_value[4:0] :
|
|
$is_srl ? $src1_value >> $src2_value[4:0] :
|
|
$is_sltu ? $sltu_rslt :
|
|
$is_sltiu ? $sltiu_rslt :
|
|
$is_lui ? {$imm[31:12], 12'b0} :
|
|
$is_auipc ? $pc + $imm :
|
|
$is_jal ? $pc + 32'd4 :
|
|
$is_jalr ? $pc + 32'd4 :
|
|
$is_srai ? {{32{$src1_value[31]}}, $src1_value} >> $imm[4:0] :
|
|
$is_slt ? (($src1_value[31] == $src2_value[31]) ? $sltu_rslt : {31'b0, $src1_value[31]}) :
|
|
$is_slti ? (($src1_value[31] == $imm[31]) ? $sltiu_rslt : {31'b0, $src1_value[31]}) :
|
|
$is_sra ? {{32{$src1_value[31]}}, $src1_value} >> $src2_value[4:0] :
|
|
'])
|
|
m4_ifelse_block(m4_reached(['LD_ST_ADDR']), ['
|
|
$is_load || $is_s_instr ? $src1_value + $imm :
|
|
'])
|
|
32'b0;
|
|
m4_define(['m4_rf_wr_en'], ['$rd_valid && ($rd != 5'b0)'])
|
|
'])
|
|
|
|
|
|
m4_ifelse_block(m4_reached(['TAKEN_BR']), ['
|
|
$taken_br = $is_beq ? ($src1_value == $src2_value) :
|
|
$is_bne ? ($src1_value != $src2_value) :
|
|
$is_blt ? (($src1_value < $src2_value) ^ ($src1_value[31] != $src2_value[31])) :
|
|
$is_bge ? (($src1_value >= $src2_value) ^ ($src1_value[31] != $src2_value[31])) :
|
|
$is_bltu ? ($src1_value < $src2_value) :
|
|
$is_bgeu ? ($src1_value >= $src2_value) :
|
|
1'b0;
|
|
|
|
$br_tgt_pc[31:0] = $pc + $imm;
|
|
'])
|
|
|
|
m4_ifelse_block(m4_reached(['ALL_INSTRS']), ['
|
|
$is_lui = $dec_bits ==? 11'bx_xxx_0110111 ;
|
|
$is_auipc = $dec_bits ==? 11'bx_xxx_0010111 ;
|
|
$is_jal = $dec_bits ==? 11'bx_xxx_1101111 ;
|
|
$is_jalr = $dec_bits ==? 11'bx_000_1100111 ;
|
|
|
|
$is_load = $opcode == 7'b0000011 ;
|
|
|
|
$is_slti = $dec_bits ==? 11'bx_010_0010011 ;
|
|
|
|
$is_sltiu = $dec_bits ==? 11'bx_011_0010011 ;
|
|
$is_xori = $dec_bits ==? 11'bx_100_0010011 ;
|
|
$is_ori = $dec_bits ==? 11'bx_110_0010011 ;
|
|
$is_andi = $dec_bits ==? 11'bx_111_0010011 ;
|
|
$is_slli = $dec_bits ==? 11'b0_001_0010011 ;
|
|
$is_srli = $dec_bits ==? 11'b0_101_0010011 ;
|
|
$is_srai = $dec_bits ==? 11'b1_101_0010011 ;
|
|
|
|
$is_sub = $dec_bits ==? 11'b1_000_0110011 ;
|
|
$is_sll = $dec_bits ==? 11'b0_001_0110011 ;
|
|
$is_slt = $dec_bits ==? 11'b0_010_0110011 ;
|
|
$is_sltu = $dec_bits ==? 11'b0_011_0110011 ;
|
|
$is_xor = $dec_bits ==? 11'b0_100_0110011 ;
|
|
$is_srl = $dec_bits ==? 11'b0_101_0110011 ;
|
|
$is_sra = $dec_bits ==? 11'b1_101_0110011 ;
|
|
$is_or = $dec_bits ==? 11'b0_110_0110011 ;
|
|
$is_and = $dec_bits ==? 11'b0_111_0110011 ;
|
|
'])
|
|
|
|
m4_ifelse_block(m4_reached(['JUMP']), ['
|
|
$jalr_tgt_pc[31:0] = $src1_value + $imm;
|
|
'])
|
|
|
|
m4_ifelse_block(m4_reached(['LD_DATA']), ['
|
|
m4_define(['m4_rf_wr_data'], ['$is_load ? $ld_data : $result'])
|
|
'])
|
|
|
|
// Assert these to end simulation (before Makerchip cycle limit).
|
|
m4_ifelse_block(m4_reached(['TB']), ['
|
|
m4+tb()
|
|
'], ['
|
|
*passed = 1'b0;
|
|
'])
|
|
*failed = *cyc_cnt > M4_MAX_CYC;
|
|
|
|
// Macro instantiations for:
|
|
// o instruction memory
|
|
// o register file
|
|
// o data memory
|
|
// o CPU visualization
|
|
//|cpu
|
|
m4_ifelse_block(m4_reached(['RF_READ']), ['
|
|
m4+rf(32, 32, $reset, m4_rf_wr_en, m4_rf_wr_index, m4_rf_wr_data, $rs1_valid, $rs1, $src1_value[31:0], $rs2_valid, $rs2, $src2_value[31:0])
|
|
'], m4_reached(['RF_MACRO']), ['
|
|
m4+rf(32, 32, $reset, $wr_en, $wr_index, $wr_data, $rd1_en, $rd1_index, $rd1_data, $rd2_en, $rd2_index, $rd2_data)
|
|
'])
|
|
m4_ifelse_block(m4_reached(['DMEM']), ['
|
|
m4+dmem(32, 32, $reset, $is_s_instr, $result[6:2], $src2_value, $is_load, $result[6:2], $ld_data)
|
|
'])
|
|
|
|
//m4+rf(32, 32, $reset, $wr_en, $wr_index, $wr_data, $rd1_en, $rd1_index, $rd1_data, $rd2_en, $rd2_index, $rd2_data)
|
|
//m4+dmem(32, 32, $reset, $wr_en, $wr_addr, $wr_data, $rd_en, $rd_addr, $wr_data)
|
|
m4+cpu_viz()
|
|
\SV
|
|
endmodule
|