58 lines
2.3 KiB
Plaintext
58 lines
2.3 KiB
Plaintext
\m4_TLV_version 1d: tl-x.org
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\SV
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// This code can be found in: https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/risc-v_shell.tlv
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m4_include_lib(['https://raw.githubusercontent.com/stevehoover/warp-v_includes/2d6d36baa4d2bc62321f982f78c8fe1456641a43/risc-v_defs.tlv'])
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m4_include_lib(['https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/main/lib/risc-v_shell_lib.tlv'])
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//---------------------------------------------------------------------------------
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// /====================\
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// | Sum 1 to 9 Program |
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// \====================/
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//
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// Program to test RV32I
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// Add 1,2,3,...,9 (in that order).
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//
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// Regs:
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// r12 (a2): 10
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// r13 (a3): 1..10
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// r14 (a4): Sum
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//
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m4_asm(ADDI, r14, r0, 0) // Initialize sum register a4 with 0
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m4_asm(ADDI, r12, r0, 1010) // Store count of 10 in register a2.
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m4_asm(ADDI, r13, r0, 1) // Initialize loop count register a3 with 0
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// Loop:
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m4_asm(ADD, r14, r13, r14) // Incremental summation
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m4_asm(ADDI, r13, r13, 1) // Increment loop count by 1
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m4_asm(BLT, r13, r12, 1111111111000) // If a3 is less than a2, branch to label named <loop>
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// Test result value in r14, and set r31 to reflect pass/fail.
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m4_asm(ADDI, r30, r14, 111111010100) // Subtract expected value of 44 to set r30 to 1 if and only iff the result is 45 (1 + 2 + ... + 9).
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m4_asm(BGE, r0, r0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
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m4_asm_end()
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m4_define(['M4_MAX_CYC'], 50)
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//---------------------------------------------------------------------------------
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\SV
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m4_makerchip_module // (Expanded in Nav-TLV pane.)
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\TLV
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$reset = *reset;
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// YOUR CODE HERE
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// ...
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// Assert these to end simulation (before Makerchip cycle limit).
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*passed = 1'b0;
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*failed = *cyc_cnt > M4_MAX_CYC;
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//m4+rf(32, 32, $reset, $wr_en, $wr_index, $wr_data, $rd1_en, $rd1_index, $rd1_data, $rd2_en, $rd2_index, $rd2_data)
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//m4+dmem(32, 32, $reset, $wr_en, $wr_addr, $wr_data, $rd_en, $rd_addr, $wr_data)
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m4+cpu_viz()
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\SV
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endmodule |