76 lines
2.8 KiB
Plaintext
76 lines
2.8 KiB
Plaintext
\m4_TLV_version 1d: tl-x.org
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\SV
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// This code can be found in: https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/risc-v_shell.tlv
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m4_include_lib(['https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/lib/risc-v_shell_lib.tlv'])
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\SV
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m4_makerchip_module // (Expanded in Nav-TLV pane.)
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\TLV
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// /====================\
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// | Sum 1 to 9 Program |
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// \====================/
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//
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// Program for MYTH Workshop to test RV32I
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// Add 1,2,3,...,9 (in that order).
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//
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// Regs:
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// r10 (a0): In: 0, Out: final sum
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// r12 (a2): 10
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// r13 (a3): 1..10
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// r14 (a4): Sum
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//
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// External to function:
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m4_asm(ADD, r10, r0, r0) // Initialize r10 (a0) to 0.
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// Function:
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m4_asm(ADD, r14, r10, r0) // Initialize sum register a4 with 0x0
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m4_asm(ADDI, r12, r10, 1010) // Store count of 10 in register a2.
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m4_asm(ADD, r13, r10, r0) // Initialize intermediate sum register a3 with 0
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// Loop:
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m4_asm(ADD, r14, r13, r14) // Incremental addition
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m4_asm(ADDI, r13, r13, 1) // Increment intermediate register by 1
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m4_asm(BLT, r13, r12, 1111111111000) // If a3 is less than a2, branch to label named <loop>
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m4_asm(ADD, r10, r14, r0) // Store final result to register a0 so that it can be read by main program
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m4_asm(ADDI, r1, r0, 101)
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m4_asm(ORI, r6, r0, 0)
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m4_asm(SW, r6, r1, 0)
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m4_asm(LW, r4, r6, 0)
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// Optional:
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m4_asm(JAL, r7, 11111111111111101000) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
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m4_define_hier(['M4_IMEM'], M4_NUM_INSTRS)
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m4+fill_imem()
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|cpu
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@0
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$reset = *reset;
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// YOUR CODE HERE
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// ...
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// Note: Because of the magic we are using for visualisation, if visualisation is enabled below,
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// be sure to avoid having unassigned signals (which you might be using for random inputs)
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// other than those specifically expected in the labs. You'll get strange errors for these.
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// Assert these to end simulation (before Makerchip cycle limit).
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*passed = *cyc_cnt > 40;
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*failed = 1'b0;
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// Macro instantiations for:
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// o instruction memory
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// o register file
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// o data memory
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// o CPU visualization
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|cpu
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m4+rf(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data, $port3_en, $port3_index, $$port3_data)
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m4+dmem(entries, width, $reset, $port1_en, $port1_index, $port1_data, $port2_en, $port2_index, $$port2_data)
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//m4+cpu_viz(@4) // For visualisation, argument should be at least equal to the last stage of CPU logic
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// @4 would work for all labs
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\SV
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endmodule
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