\m4_TLV_version 1d: tl-x.org \SV m4_include_lib(['https://raw.githubusercontent.com/stevehoover/warp-v_includes/2d6d36baa4d2bc62321f982f78c8fe1456641a43/risc-v_defs.tlv']) // v====================== lib/risc-v_shell_lib.tlv =======================v // Configuration for WARP-V definitions. m4+definitions([' m4_define_vector(['M4_WORD'], 32) m4_define(['M4_EXT_I'], 1) m4_define(['M4_NUM_INSTRS'], 0) m4_echo(m4tlv_riscv_gen__body()) // A single-line M4 macro instantiated at the end of the asm code. // It actually produces a definition of an SV macro that instantiates the IMem conaining the program (that can be parsed without \SV_plus). m4_define(['m4_asm_end'], ['`define READONLY_MEM(ADDR, DATA) assign DATA \= instrs[ADDR[\$clog2(\$size(instrs)) + 1 : 2]]; logic [31:0] instrs [0:M4_NUM_INSTRS-1]; assign instrs \= '{m4_instr0['']m4_forloop(['m4_instr_ind'], 1, M4_NUM_INSTRS, [', m4_echo(['m4_instr']m4_instr_ind)'])};']) ']) // Register File \TLV rf(_entries, _width, $_reset, $_port1_en, $_port1_index, $_port1_data, $_port2_en, $_port2_index, $_port2_data, $_port3_en, $_port3_index, $_port3_data) $rf1_wr_en = m4_argn(4, $@); $rf1_wr_index[\$clog2(_entries)-1:0] = m4_argn(5, $@); $rf1_wr_data[_width-1:0] = m4_argn(6, $@); $rf1_rd_en1 = m4_argn(7, $@); $rf1_rd_index1[\$clog2(_entries)-1:0] = m4_argn(8, $@); $rf1_rd_en2 = m4_argn(10, $@); $rf1_rd_index2[\$clog2(_entries)-1:0] = m4_argn(11, $@); /xreg[m4_eval(_entries-1):0] $wr = /top$rf1_wr_en && (/top$rf1_wr_index == #xreg); <<1$value[_width-1:0] = /top$_reset ? #xreg : $wr ? /top$rf1_wr_data : $RETAIN; $_port2_data[_width-1:0] = $rf1_rd_en1 ? /xreg[$rf1_rd_index1]$value : 'X; $_port3_data[_width-1:0] = $rf1_rd_en2 ? /xreg[$rf1_rd_index2]$value : 'X; /xreg[31:0] \viz_alpha initEach: function() { return {} // {objects: {reg: reg}}; }, renderEach: function() { siggen = (name) => this.svSigRef(`${name}`) == null ? this.svSigRef(`sticky_zero`) : this.svSigRef(`${name}`); let rf_rd_en1 = siggen(`L0_rf1_rd_en1_a0`) let rf_rd_index1 = siggen(`L0_rf1_rd_index1_a0`) let rf_rd_en2 = siggen(`L0_rf1_rd_en2_a0`) let rf_rd_index2 = siggen(`L0_rf1_rd_index2_a0`) let rf_wr_index = siggen(`rf1_wr_index_a0`) let wr = siggen(`L1_Xreg[${this.getIndex()}].L1_wr_a0`) let value = siggen(`Xreg_value_a0(${this.getIndex()})`) let rd = (rf_rd_en1.asBool(false) && rf_rd_index1.asInt() == this.getIndex()) || (rf_rd_en2.asBool(false) && rf_rd_index2.asInt() == this.getIndex()) let mod = wr.asBool(false); let wr_color = mod && rf_wr_index.asInt() == this.getIndex() let reg = parseInt(this.getIndex()) let regIdent = reg.toString().padEnd(2, " ") let newValStr = (regIdent + ": ").padEnd(14, " ") let reg_str = new fabric.Text((regIdent + ": " + value.asInt(NaN).toString()).padEnd(14, " "), { top: 18 * this.getIndex() - 40, left: 316, fontSize: 14, fill: mod ? "blue" : "black", fontWeight: mod ? 800 : 400, fontFamily: "monospace", textBackgroundColor: rd ? "#b0ffff" : wr_color ? "#ffef87" : "white" }) if (mod) { setTimeout(() => { reg_str.set({text: newValStr, textBackgroundColor: "#d0e8ff", dirty: true}) this.global.canvas.renderAll() }, 1500) } return {objects: [reg_str]} } // Data Memory \TLV dmem(_entries, _width, $_reset, $_port1_en, $_port1_index, $_port1_data, $_port2_en, $_port2_index, $_port2_data) // Allow expressions for most inputs, so define input signals. $dmem1_wr_en = m4_argn(4, $@); $dmem1_wr_index[\$clog2(_entries)-1:0] = m4_argn(5, $@); $dmem1_wr_data[_width-1:0] = m4_argn(6, $@); $dmem1_rd_en = m4_argn(7, $@); $dmem1_rd_index[\$clog2(_entries)-1:0] = m4_argn(8, $@); /dmem[m4_eval(_entries-1):0] $wr = /top$dmem1_wr_en && (/top$dmem1_wr_index == #dmem); <<1$value[_width-1:0] = /top$_reset ? 0 : $wr ? /top$dmem1_wr_data : $RETAIN; $_port2_data[_width-1:0] = $dmem1_rd_en ? /dmem[$dmem1_rd_index]$value : 'X; /dmem[m4_eval(_entries-1):0] \viz_alpha initEach: function() { return {} // {objects: {reg: reg}}; }, renderEach: function() { siggen = (name) => this.svSigRef(`${name}`) == null ? this.svSigRef(`sticky_zero`) : this.svSigRef(`${name}`); // let dmem_rd_en = siggen(`L0_dmem1_rd_en_a0`); let dmem_rd_index = siggen(`L0_dmem1_rd_index_a0`); let dmem_wr_index = siggen(`L0_dmem1_wr_index_a0`); // let wr = siggen(`L1_Dmem[${this.getIndex()}].L1_wr_a0`); let value = siggen(`Dmem_value_a0(${this.getIndex()})`); // let rd = dmem_rd_en.asBool() && dmem_rd_index.asInt() == this.getIndex(); let mod = wr.asBool(false); let wr_color = mod && dmem_wr_index.asInt() == this.getIndex(); let reg = parseInt(this.getIndex()); let regIdent = reg.toString().padEnd(2, " "); let newValStr = (regIdent + ": ").padEnd(14, " "); let dmem_str = new fabric.Text((regIdent + ": " + value.asInt(NaN).toString()).padEnd(14, " "), { top: 18 * this.getIndex() - 40, left: 480, fontSize: 14, fill: mod ? "blue" : "black", fontWeight: mod ? 800 : 400, fontFamily: "monospace", textBackgroundColor: rd ? "#b0ffff" : wr_color ? "#d0e8ff" : "white" }) if (mod) { setTimeout(() => { dmem_str.set({text: newValStr, dirty: true}) this.global.canvas.renderAll() }, 1500) } return {objects: [dmem_str]} } \TLV cpu_viz() // String representations of the instructions for debug. \SV_plus // A default signal for ones that are not found. logic sticky_zero; assign sticky_zero = 0; // Instruction strings from the assembler. logic [40*8-1:0] instr_strs [0:M4_NUM_INSTRS]; assign instr_strs = '{m4_asm_mem_expr "END "}; /cpuviz \viz_alpha initEach() { let imem_box = new fabric.Rect({ top: -50, left: -700, fill: "#208028", width: 665, height: 76 + 18 * M4_NUM_INSTRS, stroke: "black", visible: false }) let decode_box = new fabric.Rect({ top: -25, left: -15, fill: "#f8f0e8", width: 280, height: 215, stroke: "#ff8060", visible: false }) let rf_box = new fabric.Rect({ top: -90, left: 306, fill: "#2028b0", width: 145, height: 650, stroke: "black", visible: false }) let dmem_box = new fabric.Rect({ top: -90, left: 470, fill: "#208028", width: 145, height: 650, stroke: "black", visible: false }) let imem_header = new fabric.Text("🗃️ IMem", { top: -35, left: -460, fontSize: 18, fontWeight: 800, fontFamily: "monospace", fill: "white", visible: false }) let decode_header = new fabric.Text("⚙️ Instr. Decode", { top: -4, left: 20, fill: "maroon", fontSize: 18, fontWeight: 800, fontFamily: "monospace", visible: false }) let rf_header = new fabric.Text("📂 RF", { top: -75, left: 316, fontSize: 18, fontWeight: 800, fontFamily: "monospace", fill: "white", visible: false }) let dmem_header = new fabric.Text("🗃️ DMem", { top: -75, left: 480, fontSize: 18, fontWeight: 800, fontFamily: "monospace", fill: "white", visible: false }) let missing_col1 = new fabric.Text("", { top: 420, left: -480, fontSize: 16, fontWeight: 500, fontFamily: "monospace", fill: "purple" }) let missing_col2 = new fabric.Text("", { top: 420, left: -300, fontSize: 16, fontWeight: 500, fontFamily: "monospace", fill: "purple" }) let missing_sigs = new fabric.Group( [new fabric.Text("🚨 Remaining Signals for Course", { top: 350, left: -466, fontSize: 18, fontWeight: 800, fill: "red", fontFamily: "monospace" }), new fabric.Rect({ top: 400, left: -500, fill: "#ffffe0", width: 400, height: 300, stroke: "black" }), missing_col1, missing_col2, ], {visible: false} ) return {missing_col1, missing_col2, objects: {imem_box, decode_box, rf_box, dmem_box, imem_header, decode_header, rf_header, dmem_header, missing_sigs}}; }, renderEach() { // Strings (2 columns) of missing signals. var missing_list = ["", ""] var missing_cnt = 0 let sticky_zero = this.svSigRef(`sticky_zero`); // A default zero-valued signal. // Attempt to look up a signal, using sticky_zero as default and updating missing_list if expected. siggen = (name, full_name, expected = true) => { var sig = this.svSigRef(full_name ? full_name : `L0_${name}_a0`) if (sig == null) { missing_list[missing_cnt > 11 ? 1 : 0] += `◾ $${name} \n`; sig = sticky_zero; missing_cnt++ } return sig } // Look up signal, and it's ok if it doesn't exist. siggen_rf_dmem = (name, scope) => { return siggen(name, scope, false) } // Determine which is_xxx signal is asserted. siggen_mnemonic = () => { let instrs = ["lui", "auipc", "jal", "jalr", "beq", "bne", "blt", "bge", "bltu", "bgeu", "lb", "lh", "lw", "lbu", "lhu", "sb", "sh", "sw", "addi", "slti", "sltiu", "xori", "ori", "andi", "slli", "srli", "srai", "add", "sub", "sll", "slt", "sltu", "xor", "srl", "sra", "or", "and", "csrrw", "csrrs", "csrrc", "csrrwi", "csrrsi", "csrrci", "load", "store"]; for(i=0;i { return valid ? `r${regNum}` : `rX` // valid ? `r${regNum} (${regValue})` : `rX` } let immStr = (valid, immValue) => { immValue = parseInt(immValue,2) + 2*(immValue[0] << 31) return valid ? `i[${immValue}]` : ``; } let srcStr = ($src, $valid, $reg, $value) => { return $valid.asBool(false) ? `\n ${regStr(true, $reg.asInt(NaN), $value.asInt(NaN))}` : ""; } let str = `${regStr(rd_valid.asBool(false), rd.asInt(NaN), result.asInt(NaN))}\n` + ` = ${mnemonic}${srcStr(1, rs1_valid, rs1, src1_value)}${srcStr(2, rs2_valid, rs2, src2_value)}\n` + ` ${immStr(imm_valid.asBool(false), imm.asBinaryStr("0"))}`; let instrWithValues = new fabric.Text(str, { top: 70, left: 65, fill: "blue", fontSize: 14, fontFamily: "monospace", visible: instr != sticky_zero }) // Animate fetch (and provide onChange behavior for other animation). let fetch_instr_str = siggen(`instr_strs(${pc.asInt() >> 2})`, `instr_strs(${pc.asInt() >> 2})`).asString("(?) UNKNOWN fetch instr").substr(4) let fetch_instr_viz = new fabric.Text(fetch_instr_str, { top: 18 * (pc.asInt() >> 2), left: -352 + 8 * 4, fill: "black", fontSize: 14, fontFamily: "monospace", visible: instr != sticky_zero }) fetch_instr_viz.animate({top: 32, left: 10}, { onChange: this.global.canvas.renderAll.bind(this.global.canvas), duration: 500 }) // Animate RF value read/write. let src1_value_viz = new fabric.Text(src1_value.asInt(0).toString(), { left: 316 + 8 * 4, top: 18 * rs1.asInt(0) - 40, fill: "blue", fontSize: 14, fontFamily: "monospace", fontWeight: 800, visible: (src1_value != sticky_zero) && rs1_valid.asBool(false) }) setTimeout(() => {src1_value_viz.animate({left: 166, top: 70 + 18 * 2}, { onChange: this.global.canvas.renderAll.bind(this.global.canvas), duration: 500 })}, 500) let src2_value_viz = new fabric.Text(src2_value.asInt(0).toString(), { left: 316 + 8 * 4, top: 18 * rs2.asInt(0) - 40, fill: "blue", fontSize: 14, fontFamily: "monospace", fontWeight: 800, visible: (src2_value != sticky_zero) && rs2_valid.asBool(false) }) setTimeout(() => {src2_value_viz.animate({left: 166, top: 70 + 18 * 3}, { onChange: this.global.canvas.renderAll.bind(this.global.canvas), duration: 500 })}, 500) let load_viz = new fabric.Text(rf_wr_data.asInt(0).toString(), { left: 470, top: 18 * dmem_rd_index.asInt() + 6 - 40, fill: "blue", fontSize: 14, fontFamily: "monospace", fontWeight: 1000, visible: false }) if (dmem_rd_en.asBool()) { setTimeout(() => { load_viz.setVisible(true) load_viz.animate({left: 146, top: 70}, { onChange: this.global.canvas.renderAll.bind(this.global.canvas), duration: 500 }) setTimeout(() => { load_viz.setVisible(false) }, 500) }, 500) } let store_viz = new fabric.Text(src2_value.asInt(0).toString(), { left: 166, top: 70 + 18 * 3, fill: "blue", fontSize: 14, fontFamily: "monospace", fontWeight: 1000, visible: false }) if (dmem_wr_en.asBool()) { setTimeout(() => { store_viz.setVisible(true) store_viz.animate({left: 515, top: 18 * dmem_wr_index.asInt() - 40}, { onChange: this.global.canvas.renderAll.bind(this.global.canvas), duration: 500 }) }, 1000) } let result_shadow = new fabric.Text(result.asInt(0).toString(), { left: 146, top: 70, fill: "#b0b0df", fontSize: 14, fontFamily: "monospace", fontWeight: 800, visible: false }) let result_viz = new fabric.Text(rf_wr_data.asInt(0).toString(), { left: 146, top: 70, fill: "blue", fontSize: 14, fontFamily: "monospace", fontWeight: 800, visible: false }) if (rd_valid.asBool()) { setTimeout(() => { result_viz.setVisible(rf_wr_data != sticky_zero) result_shadow.setVisible(result != sticky_zero) result_viz.animate({left: 317 + 8 * 4, top: 18 * rd.asInt(0) - 40}, { onChange: this.global.canvas.renderAll.bind(this.global.canvas), duration: 500 }) }, 1000) } // Lab completion // Missing signals if (missing_list[0]) { this.getInitObject("missing_sigs").setVisible(true) this.fromInit().missing_col1.setText(missing_list[0]) this.fromInit().missing_col2.setText(missing_list[1]) } return {objects: [pcPointer, pc_arrow, ...type_texts, rs1_arrow, rs2_arrow, rd_arrow, instrWithValues, fetch_instr_viz, src1_value_viz, src2_value_viz, result_shadow, result_viz, ld_arrow, st_arrow, load_viz, store_viz]}; } /imem[m4_eval(M4_NUM_INSTRS-1):0] \viz_alpha initEach() { let binary = new fabric.Text("", { top: 18 * this.getIndex(), left: -680, fontSize: 14, fontFamily: "monospace", }) let disassembled = new fabric.Text("", { top: 18 * this.getIndex(), left: -350, fontSize: 14, fontFamily: "monospace" }) return {objects: {binary, disassembled}} }, renderEach() { // Instruction memory is constant, so just create it once. let reset = this.svSigRef(`L0_reset_a0`) let pc = this.svSigRef(`L0_pc_a0`) let rd_viz = pc && !reset.asBool() && (pc.asInt() >> 2) == this.getIndex() if (!global.instr_mem_drawn) { global.instr_mem_drawn = [] } if (!global.instr_mem_drawn[this.getIndex()]) { global.instr_mem_drawn[this.getIndex()] = true let instr = this.svSigRef(`instrs(${this.getIndex()})`) if (instr) { let binary_str = instr.asBinaryStr(NaN) this.getInitObject("binary").setText(binary_str) } let disassembled = this.svSigRef(`instr_strs(${this.getIndex()})`) if (disassembled) { let disassembled_str = disassembled.asString("") disassembled_str = disassembled_str.slice(0, -5) this.getInitObject("disassembled").setText(disassembled_str) } } this.getInitObject("disassembled").set({textBackgroundColor: rd_viz ? "#b0ffff" : "white"}) this.getInitObject("binary") .set({textBackgroundColor: rd_viz ? "#b0ffff" : "white"}) } // ^===================================================================^ \SV m4_makerchip_module // (Expanded in Nav-TLV pane.) \TLV // /====================\ // | Sum 1 to 9 Program | // \====================/ // // Program to test RV32I // Add 1,2,3,...,9 (in that order). // // Regs: // r12 (a2): 10 // r13 (a3): 1..10 // r14 (a4): Sum // m4_asm(ADDI, r14, r0, 0) // Initialize sum register a4 with 0 m4_asm(ADDI, r12, r0, 1010) // Store count of 10 in register a2. m4_asm(ADDI, r13, r0, 1) // Initialize loop count register a3 with 0 // Loop: m4_asm(ADD, r14, r13, r14) // Incremental summation m4_asm(ADDI, r13, r13, 1) // Increment loop count by 1 m4_asm(BLT, r13, r12, 1111111111000) // If a3 is less than a2, branch to label named m4_asm(SW, r6, r1, 0) m4_asm(LW, r4, r6, 0) // Optional: m4_asm(JAL, r7, 11111111111111101000) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0) m4_asm_end() //-------------------------------------- m4_default(['M4_LAB'], 10) m4_ifelse_block(m4_eval(M4_LAB > 0), ['1'], [' $reset = *reset; $next_pc[31:0] = $reset ? '0 : m4_ifelse_block(m4_eval(M4_LAB > 8), ['1'], [' $taken_br ? $br_tgt_pc : ']) m4_ifelse_block(m4_eval(M4_LAB > 12), ['1'], [' $is_jal ? $br_tgt_pc : $is_jalr ? $jalr_tgt_pc : ']) $pc + 32'd4 ; $pc[31:0] = >>1$next_pc; ']) m4_ifelse_block(m4_eval(M4_LAB > 1), ['1'], [' `READONLY_MEM($pc, $$instr[31:0]) ']) m4_ifelse_block(m4_eval(M4_LAB > 2), ['1'], [' $is_i_instr = $instr[6:2] ==? 5'b0000x || $instr[6:2] ==? 5'b001x0 || $instr[6:2] ==? 5'b11001 ; $is_r_instr = $instr[6:2] ==? 5'b01011 || $instr[6:2] ==? 5'b011x0 || $instr[6:2] ==? 5'b10100 ; $is_s_instr = $instr[6:2] ==? 5'b0100x; $is_b_instr = $instr[6:2] ==? 5'b11000; $is_j_instr = $instr[6:2] ==? 5'b11011; $is_u_instr = $instr[6:2] ==? 5'b0x101; ']) m4_ifelse_block(m4_eval(M4_LAB > 3), ['1'], [' $funct7[6:0] = $instr[31:25]; $funct3[2:0] = $instr[14:12]; $rs1[4:0] = $instr[19:15]; $rs2[4:0] = $instr[24:20]; $rd[4:0] = $instr[11:7]; $opcode[6:0] = $instr[6:0]; `BOGUS_USE($funct7 $funct3 $rs1 $rs2 $rd $opcode) $funct7_valid = $is_r_instr; $funct3_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr; $rs1_valid = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr; $rs2_valid = $is_r_instr || $is_s_instr || $is_b_instr ; $rd_valid = $is_r_instr || $is_i_instr || $is_u_instr || $is_j_instr; $imm_valid = $is_i_instr || $is_s_instr || $is_b_instr || $is_u_instr || $is_j_instr; `BOGUS_USE($funct7_valid $funct3_valid $rs1_valid $rs2_valid $rd_valid $imm_valid) ']) m4_ifelse_block(m4_eval(M4_LAB > 4), ['1'], [' $imm[31:0] = $is_i_instr ? {{21{$instr[31]}}, $instr[30:20]} : $is_s_instr ? {{21{$instr[31]}}, $instr[30:25], $instr[11:7]} : $is_b_instr ? {{20{$instr[31]}}, $instr[7], $instr[30:25], $instr[11:8], 1'b0} : $is_u_instr ? {$instr[31:12], 12'b0} : $is_j_instr ? {{12{$instr[31]}}, $instr[19:12], $instr[20], $instr[30:21], 1'b0} : 32'b0 ; `BOGUS_USE($imm) ']) m4_ifelse_block(m4_eval(M4_LAB > 5), ['1'], [' $dec_bits[10:0] = {$funct7[5], $funct3, $opcode}; $is_beq = $dec_bits ==? 11'bx_000_1100011; $is_bne = $dec_bits ==? 11'bx_001_1100011; $is_blt = $dec_bits ==? 11'bx_100_1100011; $is_bge = $dec_bits ==? 11'bx_101_1100011; $is_bltu = $dec_bits ==? 11'bx_110_1100011; $is_bgeu = $dec_bits ==? 11'bx_111_1100011; $is_addi = $dec_bits ==? 11'bx_000_0010011; $is_add = $dec_bits ==? 11'b0_000_0110011; `BOGUS_USE($is_beq $is_bne $is_blt $is_bge $is_bltu $is_bgeu $is_addi $is_add) ']) //7 - RF Read m4_define(['m4_rf_wr_en'], ['$rd_valid']) m4_define(['m4_rf_wr_data'], ['$result']) m4_ifelse_block(m4_eval(M4_LAB > 11), ['1'], [' $sltu_rslt = $src1_value < $src2_value; $sltiu_rslt = $src1_value < $imm; ']) m4_ifelse_block(m4_eval(M4_LAB > 7), ['1'], [' $result[31:0] = $is_addi ? $src1_value + $imm : $is_add ? $src1_value + $src2_value : m4_ifelse_block(m4_eval(M4_LAB > 11), ['1'], [' $is_andi ? $src1_value & $imm : $is_ori ? $src1_value | $imm : $is_xori ? $src1_value ^ $imm : $is_slli ? $src1_value << $imm[5:0] : $is_srli ? $src1_value >> $imm[5:0] : $is_and ? $src1_value & $src2_value : $is_or ? $src1_value | $src2_value : $is_xor ? $src1_value ^ $src2_value : $is_sub ? $src1_value - $src2_value : $is_sll ? $src1_value << $src2_value[4:0] : $is_srl ? $src1_value >> $src2_value[4:0] : $is_sltu ? $sltu_rslt : $is_sltiu ? $sltiu_rslt : $is_lui ? {$imm[31:12], 12'b0} : $is_auipc ? $pc + $imm : $is_jal ? $pc + 32'd4 : $is_jalr ? $pc + 32'd4 : $is_srai ? {{32{$src1_value[31]}}, $src1_value} >> $imm[4:0] : $is_slt ? (($src1_value[31] == $src2_value[31]) ? $sltu_rslt : {31'b0, $src1_value[31]}) : $is_slti ? (($src1_value[31] == $imm[31]) ? $sltiu_rslt : {31'b0, $src1_value[31]}) : $is_sra ? {{32{$src1_value[31]}}, $src1_value} >> $src2_value[4:0] : ']) m4_ifelse_block(m4_eval(M4_LAB > 99), ['1'], [' $is_load || $is_s_instr ? $src1_value + $imm : ']) 32'bx; m4_define(['m4_rf_wr_en'], ['$rd_valid && ($rd != 5'b0)']) ']) m4_ifelse_block(m4_eval(M4_LAB > 8), ['1'], [' $taken_br = $is_beq ? ($src1_value == $src2_value) : $is_bne ? ($src1_value != $src2_value) : $is_blt ? (($src1_value < $src2_value) ^ ($src1_value[31] != $src2_value[31])) : $is_bge ? (($src1_value >= $src2_value) ^ ($src1_value[31] != $src2_value[31])) : $is_bltu ? ($src1_value < $src2_value) : $is_bgeu ? ($src1_value >= $src2_value) : 1'b0; $br_tgt_pc[31:0] = $pc + $imm; ']) m4_ifelse_block(m4_eval(M4_LAB > 10), ['1'], [' $is_lui = $dec_bits ==? 11'bx_xxx_0110111 ; $is_auipc = $dec_bits ==? 11'bx_xxx_0010111 ; $is_jal = $dec_bits ==? 11'bx_xxx_1101111 ; $is_jalr = $dec_bits ==? 11'bx_000_1100111 ; $is_load = $opcode == 7'b0000011 ; $is_slti = $dec_bits ==? 11'bx_010_0010011 ; $is_sltiu = $dec_bits ==? 11'bx_011_0010011 ; $is_xori = $dec_bits ==? 11'bx_100_0010011 ; $is_ori = $dec_bits ==? 11'bx_110_0010011 ; $is_andi = $dec_bits ==? 11'bx_111_0010011 ; $is_slli = $dec_bits ==? 11'b0_001_0010011 ; $is_srli = $dec_bits ==? 11'b0_101_0010011 ; $is_srai = $dec_bits ==? 11'b1_101_0010011 ; $is_sub = $dec_bits ==? 11'b1_000_0110011 ; $is_sll = $dec_bits ==? 11'b0_001_0110011 ; $is_slt = $dec_bits ==? 11'b0_010_0110011 ; $is_sltu = $dec_bits ==? 11'b0_011_0110011 ; $is_xor = $dec_bits ==? 11'b0_100_0110011 ; $is_srl = $dec_bits ==? 11'b0_101_0110011 ; $is_sra = $dec_bits ==? 11'b1_101_0110011 ; $is_or = $dec_bits ==? 11'b0_110_0110011 ; $is_and = $dec_bits ==? 11'b0_111_0110011 ; ']) m4_ifelse_block(m4_eval(M4_LAB > 12), ['1'], [' $is_jump = $is_jal || $is_jalr; $jalr_tgt_pc[31:0] = $src1_value + $imm; ']) //14 - DMem m4_ifelse_block(m4_eval(M4_LAB > 13), ['1'], [' m4_define(['m4_rf_wr_data'] ['$is_load ? $ld_data : $result']) ']) // Assert these to end simulation (before Makerchip cycle limit). m4_ifelse_block(m4_eval(M4_LAB > 9), ['1'], [' *passed = /xreg[14]$value == (1+2+3+4+5+6+7+8+9); '], [' *passed = *cyc_cnt > 50; ']) *failed = 1'b0; // Macro instantiations for: // o instruction memory // o register file // o data memory // o CPU visualization //|cpu m4_ifelse_block(m4_eval(M4_LAB > 6), ['1'], [' m4+rf(32, 32, $reset, m4_rf_wr_en, $rd, m4_rf_wr_data, $rs1_valid, $rs1, $src1_value[31:0], $rs2_valid, $rs2, $src2_value[31:0]) ']) //m4+rf(32, 32, $reset, $rd_valid && ($rd != 5'b0), $rd, $result, $rs1_valid, $rs1, $src1_value[31:0], $rs2_valid, $rs2, $src2_value[31:0]) m4_ifelse_block(m4_eval(M4_LAB > 13), ['1'], [' m4+dmem(32, 32, $reset, $is_s_instr, $result[6:2], $src2_value, $is_load, $result[6:2], $ld_data[31:0]) ']) m4+cpu_viz() \SV endmodule