Add data memory and implement store/load

Added $ to missing signals VIZ.

lib/calc_viz.tlv

@@ -1,12 +1,5 @@
 \m4_TLV_version 1d: tl-x.org
 \SV
-
-   // =========================================
-   // Welcome!  Try the tutorials via the menu.
-   // =========================================
-
-   // Default Makerchip TL-Verilog Code Template
-   
    // Macro providing required top-level module definition, random
    // stimulus support, and Verilator config.
    m4_makerchip_module   // (Expanded in Nav-TLV pane.)
@@ -14,13 +7,13 @@
 
 // Visualization for calculator
 \TLV calc_viz()
-   // m4_ifelse_block(m4_sp_graph_dangerous, 1, , {{
    \SV_plus
       logic sticky_zero;
       assign sticky_zero = 0;
    /view
-      \viz_alpha
+      \viz_js
-         initEach() {
+         box: {strokeWidth: 0},
+         init() {
             let hexcalname = new fabric.Text("HEX Calc 3000", {
               left: -150 + 150,
               top: -150 + 40,
@@ -157,7 +150,7 @@
               fontSize: 22,
               fontFamily: "Courier New",
             })
-            let missing = new fabric.Text("", {
+            this.missing = new fabric.Text("", {
                   top: 360,
                   left: -160,
                   fontSize: 16,
@@ -182,24 +175,23 @@
                   height: 300,
                   stroke: "black"
                 }),
-                missing
+                this.missing
                ],
                {visible: false}
               )
             
-            return {missing,
+            return {calbox, val1box, val1num, val2box, val2num,
-                    objects: {calbox, val1box, val1num, val2box, val2num,
+                    outbox, outnum, equalname, sumbox, minbox, prodbox, quotbox, sumicon,
-                              outbox, outnum, equalname, sumbox, minbox, prodbox, quotbox, sumicon,
+                    prodicon, minicon: minicon, quoticon: quoticon, hexcalname, missing_sigs}
-                              prodicon, minicon: minicon, quoticon: quoticon, hexcalname, missing_sigs}};
          },
-         renderEach() {
+         render() {
             let missing_list = "";
             let sig_names = ["op", "val1", "val2", "out"];
             let sticky_zero = this.svSigRef(`sticky_zero`);
             getSig = (name) => {
                let sig = this.svSigRef(`L0_${name}_a0`);
                if (sig == null) {
-                  missing_list += `◾ ${name}      \n`;
+                  missing_list += `◾ $${name}      \n`;
                   sig         = sticky_zero;
                }
                return sig;
@@ -208,18 +200,18 @@
                result[sig_name] = getSig(sig_name)
                return result
             }, {})
-            this.getInitObject("val1num").set({text: sigs.val1.asInt(NaN).toString(16).padStart(8, " ")})
+            this.getObjects().val1num.set({text: sigs.val1.asInt(NaN).toString(16).padStart(8, " ")})
-            this.getInitObject("val2num").set({text: sigs.val2.asInt(NaN).toString(16).padStart(8, " ")})
+            this.getObjects().val2num.set({text: sigs.val2.asInt(NaN).toString(16).padStart(8, " ")})
-            this.getInitObject("outnum").set({text: sigs.out.asInt(NaN).toString(16).padStart(8, " ")})
+            this.getObjects().outnum.set({text: sigs.out.asInt(NaN).toString(16).padStart(8, " ")})
             let op = sigs.op.asInt(NaN)
-            this.getInitObject("sumbox").set({fill: op == 0 ?  "#c0d0e0" : "#a0a0a0"})
+            this.getObjects().sumbox.set({fill: op == 0 ?  "#c0d0e0" : "#a0a0a0"})
-            this.getInitObject("minbox").set({fill: op == 1 ?  "#c0d0e0" : "#a0a0a0"})
+            this.getObjects().minbox.set({fill: op == 1 ?  "#c0d0e0" : "#a0a0a0"})
-            this.getInitObject("prodbox").set({fill: op == 2 ? "#c0d0e0" : "#a0a0a0"})
+            this.getObjects().prodbox.set({fill: op == 2 ? "#c0d0e0" : "#a0a0a0"})
-            this.getInitObject("quotbox").set({fill: op == 3 ? "#c0d0e0" : "#a0a0a0"})
+            this.getObjects().quotbox.set({fill: op == 3 ? "#c0d0e0" : "#a0a0a0"})
             if (missing_list) {
-               this.getInitObject("calbox").set({fill: "red"})
+               this.getObjects().calbox.set({fill: "red"})
-               this.getInitObject("missing_sigs").set({visible:true})
+               this.getObjects().missing_sigs.set({visible:true})
-               this.fromInit().missing.set({text: missing_list})
+               this.missing.set({text: missing_list})
             }
          }
 \TLV

risc-v_shell.tlv

@@ -36,6 +36,8 @@
    // Program counter
    $next_pc[31:0] = $reset ? 0 :
       $taken_br ? $br_tgt_pc :
+      $is_jal ? $br_tgt_pc :
+      $is_jalr ? $jalr_tgt_pc :
       ($pc + 4);
    $pc[31:0] = >>1$next_pc;
 
@@ -92,7 +94,8 @@
    $is_lui = $dec_bits ==? 11'bx_xxx_011_0111;
    $is_auipc = $dec_bits ==? 11'bx_xxx_001_0111;
    $is_jal = $dec_bits ==? 11'bx_xxx_110_1111;
-   $is_slti = $dec_bits ==? 11'bx_010_011_0011;
+   $is_jalr = $dec_bits ==? 11'bx_000_110_0111;
+   $is_slti = $dec_bits ==? 11'bx_010_001_0011;
    $is_sltiu = $dec_bits ==? 11'bx_011_001_0011;
    $is_xori = $dec_bits ==? 11'bx_100_001_0011;
    $is_ori = $dec_bits ==? 11'bx_110_001_0011;
@@ -112,7 +115,6 @@
 
    // Treat all load and store instructions the same
    $is_load = $dec_bits ==? 11'bx_xxx_000_0011;
-   $is_s_instr = $dec_bits ==? 11'bx_xxx_010_0011;
 
    // Compute whether to branch
    $taken_br = $is_beq ? $src1_value == $src2_value :
@@ -123,13 +125,50 @@
       $is_bgeu ? $src1_value >= $src2_value :
       0;
 
-   // Branch target
+   // Branch/JAL target
    $br_tgt_pc[31:0] = $pc + $imm;
 
+   // Jump and link register target
+   $jalr_tgt_pc[31:0] = $src1_value + $imm;
+
    // Arithmetic Logic Unit
+   $sltu_rslt[31:0] = {31'b0, $src1_value < $src2_value};
+   $sltiu_rslt[31:0] = {31'b0, $src1_value < $imm};
+
+   $sext_src1[63:0] = { {32{$src1_value[31]}}, $src1_value };
+   $sra_rslt[63:0] = $sext_src1 >> $src2_value[4:0];
+   $srai_rslt[63:0] = $sext_src1 >> $imm[4:0];
+
    $result[31:0] =
+      $is_andi ? $src1_value & $imm :
+      $is_ori ? $src1_value | $imm :
+      $is_xori ? $src1_value ^ $imm :
       $is_addi ? $src1_value + $imm :
+      $is_slli ? $src1_value << $imm[5:0] :
+      $is_srli ? $src1_value >> $imm[5:0] :
+      $is_and ? $src1_value & $src2_value :
+      $is_or ? $src1_value | $src2_value :
+      $is_xor ? $src1_value ^ $src2_value :
       $is_add ? $src1_value + $src2_value :
+      $is_sub ? $src1_value - $src2_value :
+      $is_sll ? $src1_value << $src2_value[4:0] :
+      $is_srl ? $src1_value >> $src2_value[4:0] :
+      $is_sltu ? $sltu_rslt :
+      $is_sltiu ? $sltiu_rslt :
+      $is_lui ? {$imm[31:12], 12'b0} :
+      $is_auipc ? $pc + $imm :
+      $is_jal ? $pc + 32'd4 :
+      $is_jalr ? $pc + 32'd4 :
+      $is_slt ? ( ($src1_value[31] == $src2_value[31]) ?
+         $sltu_rslt :
+         {31'b0, $src1_value[31]} ) :
+      $is_slti ? ( ($src1_value[31] == $imm[31]) ?
+         $sltiu_rslt :
+         {31'b0, $src1_value[31]} ) :
+      $is_sra ? $sra_rslt[31:0] :
+      $is_srai ? $srai_rslt[31:0] :
+      $is_load  ? $src1_value + $imm :
+      $is_s_instr ? $src1_value + $imm :
       32'b0;
 
    // Assert these to end simulation (before Makerchip cycle limit).
@@ -137,8 +176,9 @@
    *failed = *cyc_cnt > M4_MAX_CYC;
 
    // Register file
-   m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $result, $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
+   $rf_data[31:0] = $is_load ? $ld_data : $result;
-   //m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
+   m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $rf_data, $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
+   m4+dmem(32, 32, $reset, $result[4:0], $is_s_instr, $src2_value, $is_load, $ld_data)
    m4+cpu_viz()
 \SV
    endmodule