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7 Commits
97e7881dbe
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ff0ec641d2
| Author | SHA1 | Date |
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 Victor Timofei
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ff0ec641d2
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Victor Timofei
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d2b945d974
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Victor Timofei
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ce288f2840 | |
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Victor Timofei
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c98b2fc672
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Victor Timofei
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26bc694325
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Steve Hoover
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dcd5e407e3 | |
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Steve Hoover
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dac60392eb |
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@ -1,12 +1,5 @@
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\m4_TLV_version 1d: tl-x.org
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\SV
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// =========================================
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// Welcome! Try the tutorials via the menu.
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// =========================================
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// Default Makerchip TL-Verilog Code Template
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// Macro providing required top-level module definition, random
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// stimulus support, and Verilator config.
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m4_makerchip_module // (Expanded in Nav-TLV pane.)
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@ -14,13 +7,13 @@
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// Visualization for calculator
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\TLV calc_viz()
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// m4_ifelse_block(m4_sp_graph_dangerous, 1, , {{
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\SV_plus
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logic sticky_zero;
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assign sticky_zero = 0;
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/view
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\viz_alpha
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initEach() {
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\viz_js
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box: {strokeWidth: 0},
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init() {
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let hexcalname = new fabric.Text("HEX Calc 3000", {
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left: -150 + 150,
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top: -150 + 40,
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@ -157,7 +150,7 @@
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fontSize: 22,
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fontFamily: "Courier New",
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})
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let missing = new fabric.Text("", {
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this.missing = new fabric.Text("", {
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top: 360,
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left: -160,
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fontSize: 16,
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@ -182,24 +175,23 @@
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height: 300,
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stroke: "black"
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}),
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missing
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this.missing
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],
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{visible: false}
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)
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return {missing,
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objects: {calbox, val1box, val1num, val2box, val2num,
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outbox, outnum, equalname, sumbox, minbox, prodbox, quotbox, sumicon,
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prodicon, minicon: minicon, quoticon: quoticon, hexcalname, missing_sigs}};
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return {calbox, val1box, val1num, val2box, val2num,
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outbox, outnum, equalname, sumbox, minbox, prodbox, quotbox, sumicon,
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prodicon, minicon: minicon, quoticon: quoticon, hexcalname, missing_sigs}
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},
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renderEach() {
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render() {
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let missing_list = "";
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let sig_names = ["op", "val1", "val2", "out"];
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let sticky_zero = this.svSigRef(`sticky_zero`);
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getSig = (name) => {
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let sig = this.svSigRef(`L0_${name}_a0`);
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if (sig == null) {
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missing_list += `◾ ${name} \n`;
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missing_list += `◾ $${name} \n`;
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sig = sticky_zero;
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}
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return sig;
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@ -208,18 +200,18 @@
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result[sig_name] = getSig(sig_name)
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return result
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}, {})
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this.getInitObject("val1num").set({text: sigs.val1.asInt(NaN).toString(16).padStart(8, " ")})
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this.getInitObject("val2num").set({text: sigs.val2.asInt(NaN).toString(16).padStart(8, " ")})
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this.getInitObject("outnum").set({text: sigs.out.asInt(NaN).toString(16).padStart(8, " ")})
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this.getObjects().val1num.set({text: sigs.val1.asInt(NaN).toString(16).padStart(8, " ")})
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this.getObjects().val2num.set({text: sigs.val2.asInt(NaN).toString(16).padStart(8, " ")})
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this.getObjects().outnum.set({text: sigs.out.asInt(NaN).toString(16).padStart(8, " ")})
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let op = sigs.op.asInt(NaN)
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this.getInitObject("sumbox").set({fill: op == 0 ? "#c0d0e0" : "#a0a0a0"})
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this.getInitObject("minbox").set({fill: op == 1 ? "#c0d0e0" : "#a0a0a0"})
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this.getInitObject("prodbox").set({fill: op == 2 ? "#c0d0e0" : "#a0a0a0"})
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this.getInitObject("quotbox").set({fill: op == 3 ? "#c0d0e0" : "#a0a0a0"})
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this.getObjects().sumbox.set({fill: op == 0 ? "#c0d0e0" : "#a0a0a0"})
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this.getObjects().minbox.set({fill: op == 1 ? "#c0d0e0" : "#a0a0a0"})
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this.getObjects().prodbox.set({fill: op == 2 ? "#c0d0e0" : "#a0a0a0"})
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this.getObjects().quotbox.set({fill: op == 3 ? "#c0d0e0" : "#a0a0a0"})
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if (missing_list) {
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this.getInitObject("calbox").set({fill: "red"})
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this.getInitObject("missing_sigs").set({visible:true})
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this.fromInit().missing.set({text: missing_list})
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this.getObjects().calbox.set({fill: "red"})
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this.getObjects().missing_sigs.set({visible:true})
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this.missing.set({text: missing_list})
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}
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}
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\TLV
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File diff suppressed because it is too large
Load Diff
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@ -36,6 +36,8 @@
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// Program counter
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$next_pc[31:0] = $reset ? 0 :
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$taken_br ? $br_tgt_pc :
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$is_jal ? $br_tgt_pc :
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$is_jalr ? $jalr_tgt_pc :
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($pc + 4);
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$pc[31:0] = >>1$next_pc;
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@ -92,7 +94,8 @@
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$is_lui = $dec_bits ==? 11'bx_xxx_011_0111;
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$is_auipc = $dec_bits ==? 11'bx_xxx_001_0111;
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$is_jal = $dec_bits ==? 11'bx_xxx_110_1111;
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$is_slti = $dec_bits ==? 11'bx_010_011_0011;
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$is_jalr = $dec_bits ==? 11'bx_000_110_0111;
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$is_slti = $dec_bits ==? 11'bx_010_001_0011;
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$is_sltiu = $dec_bits ==? 11'bx_011_001_0011;
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$is_xori = $dec_bits ==? 11'bx_100_001_0011;
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$is_ori = $dec_bits ==? 11'bx_110_001_0011;
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@ -112,7 +115,6 @@
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// Treat all load and store instructions the same
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$is_load = $dec_bits ==? 11'bx_xxx_000_0011;
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$is_s_instr = $dec_bits ==? 11'bx_xxx_010_0011;
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// Compute whether to branch
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$taken_br = $is_beq ? $src1_value == $src2_value :
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@ -123,13 +125,50 @@
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$is_bgeu ? $src1_value >= $src2_value :
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0;
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// Branch target
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// Branch/JAL target
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$br_tgt_pc[31:0] = $pc + $imm;
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// Jump and link register target
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$jalr_tgt_pc[31:0] = $src1_value + $imm;
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// Arithmetic Logic Unit
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$sltu_rslt[31:0] = {31'b0, $src1_value < $src2_value};
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$sltiu_rslt[31:0] = {31'b0, $src1_value < $imm};
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$sext_src1[63:0] = { {32{$src1_value[31]}}, $src1_value };
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$sra_rslt[63:0] = $sext_src1 >> $src2_value[4:0];
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$srai_rslt[63:0] = $sext_src1 >> $imm[4:0];
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$result[31:0] =
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$is_andi ? $src1_value & $imm :
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$is_ori ? $src1_value | $imm :
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$is_xori ? $src1_value ^ $imm :
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$is_addi ? $src1_value + $imm :
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$is_slli ? $src1_value << $imm[5:0] :
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$is_srli ? $src1_value >> $imm[5:0] :
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$is_and ? $src1_value & $src2_value :
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$is_or ? $src1_value | $src2_value :
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$is_xor ? $src1_value ^ $src2_value :
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$is_add ? $src1_value + $src2_value :
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$is_sub ? $src1_value - $src2_value :
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$is_sll ? $src1_value << $src2_value[4:0] :
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$is_srl ? $src1_value >> $src2_value[4:0] :
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$is_sltu ? $sltu_rslt :
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$is_sltiu ? $sltiu_rslt :
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$is_lui ? {$imm[31:12], 12'b0} :
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$is_auipc ? $pc + $imm :
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$is_jal ? $pc + 32'd4 :
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$is_jalr ? $pc + 32'd4 :
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$is_slt ? ( ($src1_value[31] == $src2_value[31]) ?
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$sltu_rslt :
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{31'b0, $src1_value[31]} ) :
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$is_slti ? ( ($src1_value[31] == $imm[31]) ?
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$sltiu_rslt :
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{31'b0, $src1_value[31]} ) :
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$is_sra ? $sra_rslt[31:0] :
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$is_srai ? $srai_rslt[31:0] :
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$is_load ? $src1_value + $imm :
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$is_s_instr ? $src1_value + $imm :
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32'b0;
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// Assert these to end simulation (before Makerchip cycle limit).
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@ -137,8 +176,9 @@
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*failed = *cyc_cnt > M4_MAX_CYC;
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// Register file
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m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $result, $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
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//m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
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$rf_data[31:0] = $is_load ? $ld_data : $result;
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m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $rf_data, $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
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m4+dmem(32, 32, $reset, $result[4:0], $is_s_instr, $src2_value, $is_load, $ld_data)
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m4+cpu_viz()
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\SV
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endmodule
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