Add data memory and implement store/load
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@ -115,7 +115,6 @@
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// Treat all load and store instructions the same
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// Treat all load and store instructions the same
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$is_load = $dec_bits ==? 11'bx_xxx_000_0011;
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$is_load = $dec_bits ==? 11'bx_xxx_000_0011;
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$is_s_instr = $dec_bits ==? 11'bx_xxx_010_0011;
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// Compute whether to branch
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// Compute whether to branch
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$taken_br = $is_beq ? $src1_value == $src2_value :
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$taken_br = $is_beq ? $src1_value == $src2_value :
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@ -168,6 +167,8 @@
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{31'b0, $src1_value[31]} ) :
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{31'b0, $src1_value[31]} ) :
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$is_sra ? $sra_rslt[31:0] :
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$is_sra ? $sra_rslt[31:0] :
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$is_srai ? $srai_rslt[31:0] :
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$is_srai ? $srai_rslt[31:0] :
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$is_load ? $src1_value + $imm :
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$is_s_instr ? $src1_value + $imm :
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32'b0;
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32'b0;
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// Assert these to end simulation (before Makerchip cycle limit).
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// Assert these to end simulation (before Makerchip cycle limit).
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@ -175,8 +176,9 @@
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*failed = *cyc_cnt > M4_MAX_CYC;
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*failed = *cyc_cnt > M4_MAX_CYC;
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// Register file
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// Register file
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m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $result, $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
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$rf_data[31:0] = $is_load ? $ld_data : $result;
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//m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data)
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m4+rf(32, 32, $reset, $rd_valid, $rd[4:0], $rf_data, $rs1_valid, $rs1[4:0], $src1_value, $rs2_valid, $rs2[4:0], $src2_value)
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m4+dmem(32, 32, $reset, $result[4:0], $is_s_instr, $src2_value, $is_load, $ld_data)
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m4+cpu_viz()
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m4+cpu_viz()
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\SV
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\SV
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endmodule
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endmodule
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