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LF-Building-a-RISC-V-CPU-Core
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fix

This commit is contained in:
Steve Hoover 2021-02-09 19:13:38 -05:00
parent d3872a0fe1
commit f9047e6dc0
1 changed files with 1 additions and 1 deletions
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2
lib/risc-v_shell_lib.tlv
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@ -180,7 +180,7 @@ m4+definitions(['
let rf_rd_index1 = siggen_rf_dmem("rf_rd_index1") let rf_rd_index1 = siggen_rf_dmem("rf_rd_index1")
let rf_rd_en2 = siggen_rf_dmem("rf_rd_en2") let rf_rd_en2 = siggen_rf_dmem("rf_rd_en2")
let rf_rd_index2 = siggen_rf_dmem("rf_rd_index2") let rf_rd_index2 = siggen_rf_dmem("rf_rd_index2")
let rf_wr_en = siggen_rf_dmem("rf_wr_en" let rf_wr_en = siggen_rf_dmem("rf_wr_en")
let rf_wr_index = siggen_rf_dmem("rf_wr_index") let rf_wr_index = siggen_rf_dmem("rf_wr_index")
let rf_wr_data = siggen_rf_dmem("rf_wr_data") let rf_wr_data = siggen_rf_dmem("rf_wr_data")
let dmem_rd_en = siggen_rf_dmem("dmem_rd_en") let dmem_rd_en = siggen_rf_dmem("dmem_rd_en")