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LF-Building-a-RISC-V-CPU-Core
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minor.

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Steve Hoover 2021-02-27 15:38:14 -05:00
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commit d2e0c8cbcf
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risc-v_shell.tlv
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@ -54,7 +54,6 @@
//m4+rf(32, 32, $reset, $wr_en, $wr_index, $wr_data, $rd1_en, $rd1_index, $rd1_data, $rd2_en, $rd2_index, $rd2_data) //m4+rf(32, 32, $reset, $wr_en, $wr_index, $wr_data, $rd1_en, $rd1_index, $rd1_data, $rd2_en, $rd2_index, $rd2_data)
//m4+dmem(32, 32, $reset, $wr_en, $wr_addr, $wr_data, $rd_en, $rd_addr, $wr_data) //m4+dmem(32, 32, $reset, $wr_en, $wr_addr, $wr_data, $rd_en, $rd_addr, $wr_data)
//m4+test_prog()
m4+cpu_viz() m4+cpu_viz()
\SV \SV
endmodule endmodule