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LF-Building-a-RISC-V-CPU-Core
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Complete ALU

This commit is contained in:
Victor Timofei 2022-01-16 14:22:57 +02:00
parent 26bc694325
commit c98b2fc672
Signed by: vtimofei
GPG Key ID: B790DCEBE281403A
1 changed files with 32 additions and 0 deletions
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32
risc-v_shell.tlv
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@ -128,9 +128,41 @@
$br_tgt_pc[31:0] = $pc + $imm; $br_tgt_pc[31:0] = $pc + $imm;
// Arithmetic Logic Unit // Arithmetic Logic Unit
$sltu_rslt[31:0] = {31'b0, $src1_value < $src2_value};
$sltiu_rslt[31:0] = {31'b0, $src1_value < $imm};
$sext_src1[63:0] = { {32{$src1_value[31]}}, $src1_value };
$sra_rslt[63:0] = $sext_src1 >> $src2_value[4:0];
$srai_rslt[63:0] = $sext_src1 >> $imm[4:0];
$result[31:0] = $result[31:0] =
$is_andi ? $src1_value & $imm :
$is_ori ? $src1_value | $imm :
$is_xori ? $src1_value ^ $imm :
$is_addi ? $src1_value + $imm : $is_addi ? $src1_value + $imm :
$is_slli ? $src1_value << $imm[5:0] :
$is_srli ? $src1_value >> $imm[5:0] :
$is_and ? $src1_value & $src2_value :
$is_or ? $src1_value | $src2_value :
$is_xor ? $src1_value ^ $src2_value :
$is_add ? $src1_value + $src2_value : $is_add ? $src1_value + $src2_value :
$is_sub ? $src1_value - $src2_value :
$is_sll ? $src1_value << $src2_value[4:0] :
$is_srl ? $src1_value >> $src2_value[4:0] :
$is_sltu ? $sltu_rslt :
$is_sltiu ? $sltiu_rslt :
$is_lui ? {$imm[31:12], 12'b0} :
$is_auipc ? $pc + $imm :
$is_jal ? $pc + 32'd4 :
$is_jalr ? $pc + 32'd4 :
$is_slt ? ( ($src1_value[31] == $src2_value[31]) ?
$sltu_rslt :
{31'b0, $src1_value[31]} ) :
$is_slti ? ( ($src1_value[31] == $imm[31]) ?
$sltiu_rslt :
{31'b0, $src1_value[31]} ) :
$is_sra ? $sra_rslt[31:0] :
$is_srai ? $srai_rslt[31:0] :
32'b0; 32'b0;
// Assert these to end simulation (before Makerchip cycle limit). // Assert these to end simulation (before Makerchip cycle limit).