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LF-Building-a-RISC-V-CPU-Core
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Providing bit widths on array macro inputs.

This commit is contained in:
Steve Hoover 2021-02-27 19:05:01 -05:00
parent b24f7ea69f
commit c2b5ff0171
1 changed files with 2 additions and 2 deletions
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4
risc-v_shell.tlv
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@ -52,8 +52,8 @@
*passed = 1'b0;
*failed = *cyc_cnt > M4_MAX_CYC;
//m4+rf(32, 32, $reset, $wr_en, $wr_index, $wr_data, $rd1_en, $rd1_index, $rd1_data, $rd2_en, $rd2_index, $rd2_data)
//m4+dmem(32, 32, $reset, $wr_en, $wr_addr, $wr_data, $rd_en, $rd_addr, $wr_data)
//m4+rf(32, 32, $reset, $wr_en, $wr_index[4:0], $wr_data[31:0], $rd1_en, $rd1_index[4:0], $rd1_data, $rd2_en, $rd2_index[4:0], $rd2_data)
//m4+dmem(32, 32, $reset, $wr_en, $wr_addr[4:0], $wr_data[31:0], $rd_en, $rd_addr[4:0], $wr_data)
m4+cpu_viz()
\SV
endmodule