vtimofei
/
LF-Building-a-RISC-V-CPU-Core
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Include //m4+test_prog in shell because it must be instantiated in the right place.

This commit is contained in:
Steve Hoover 2021-02-26 18:33:23 -05:00
parent 09f187f917
commit 93d3108a30
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
risc-v_shell.tlv
View File

@ -53,6 +53,7 @@
//m4+rf(32, 32, $reset, $wr_en, $wr_index, $wr_data, $rd1_en, $rd1_index, $rd1_data, $rd2_en, $rd2_index, $rd2_data) //m4+rf(32, 32, $reset, $wr_en, $wr_index, $wr_data, $rd1_en, $rd1_index, $rd1_data, $rd2_en, $rd2_index, $rd2_data)
//m4+dmem(32, 32, $reset, $wr_en, $wr_addr, $wr_data, $rd_en, $rd_addr, $wr_data) //m4+dmem(32, 32, $reset, $wr_en, $wr_addr, $wr_data, $rd_en, $rd_addr, $wr_data)
//m4+test_prog()
m4+cpu_viz() m4+cpu_viz()
\SV \SV
endmodule endmodule