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LF-Building-a-RISC-V-CPU-Core
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Victor Timofei 2022-01-11 21:58:01 +02:00
parent 7085ac35bc
commit 8fc1626ae3
Signed by: vtimofei
GPG Key ID: B790DCEBE281403A
1 changed files with 1 additions and 12 deletions
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risc-v_shell.tlv
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@ -20,18 +20,7 @@
// x13 (a3): 1..10
// x14 (a4): Sum
//
m4_asm(ADDI, x14, x0, 0) // Initialize sum register a4 with 0
m4_asm(ADDI, x12, x0, 1010) // Store count of 10 in register a2.
m4_asm(ADDI, x13, x0, 1) // Initialize loop count register a3 with 0
// Loop:
m4_asm(ADD, x14, x13, x14) // Incremental summation
m4_asm(ADDI, x13, x13, 1) // Increment loop count by 1
m4_asm(BLT, x13, x12, 1111111111000) // If a3 is less than a2, branch to label named <loop>
// Test result value in x14, and set x31 to reflect pass/fail.
m4_asm(ADDI, x30, x14, 111111010100) // Subtract expected value of 44 to set x30 to 1 if and only iff the result is 45 (1 + 2 + ... + 9).
m4_asm(BGE, x0, x0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
m4_asm_end()
m4_define(['M4_MAX_CYC'], 50)
m4_test_prog()
//---------------------------------------------------------------------------------