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LF-Building-a-RISC-V-CPU-Core
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Implement branch

This commit is contained in:
Victor Timofei 2022-01-11 21:44:11 +02:00
parent a7d3c26f76
commit 6c08931ddd
Signed by: vtimofei
GPG Key ID: B790DCEBE281403A
1 changed files with 15 additions and 1 deletions
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16
risc-v_shell.tlv
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@ -45,7 +45,9 @@
// Program counter
$next_pc[31:0] = $reset ? 0 : ($pc + 4);
$next_pc[31:0] = $reset ? 0 :
$taken_br ? $br_tgt_pc :
($pc + 4);
$pc[31:0] = >>1$next_pc;
// Instruction memory
@ -104,6 +106,18 @@
*passed = 1'b0;
*failed = *cyc_cnt > M4_MAX_CYC;
// Compute whether to branch
$taken_br = $is_beq ? $src1_value == $src2_value :
$is_bne ? $src1_value != $src2_value :
$is_blt ? ($src1_value < $src2_value) ^ ($src1_value[31] != $src2_value[31]) :
$is_bge ? ($src1_value >= $src2_value) ^ ($src1_value[31] != $src2_value[31]) :
$is_bltu ? $src1_value < $src2_value :
$is_bgeu ? $src1_value >= $src2_value :
0;
// Branch target
$br_tgt_pc[31:0] = $pc + $imm;
// Arithmetic Logic Unit
$result[31:0] =
$is_addi ? $src1_value + $imm :