Reworking the way test_prog works.
This commit is contained in:
Steve Hoover
parent
93d3108a30
commit
67042549b7
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@ -6,6 +6,100 @@
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// Configuration for WARP-V definitions.
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// Configuration for WARP-V definitions.
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m4+definitions(['
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m4+definitions(['
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// Define full test program.
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// Provide a non-empty argument if this is instantiated within a \TLV region (vs. \SV).
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m4_define(['m4_test_prog'], ['m4_hide(['
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// /=======================\
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// | Test each instruction |
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// \=======================/
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//
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// Some constant values to use as operands.
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m4_asm(ADDI, x1, x0, 10101) // An operand value of 21.
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m4_asm(ADDI, x2, x0, 111) // An operand value of 7.
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m4_asm(ADDI, x3, x0, 111111111100) // An operand value of -4.
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// Execute one of each instruction, XORing subtracting (via ADDI) the expected value.
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// ANDI:
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m4_asm(ANDI, x5, x1, 1011100)
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m4_asm(XORI, x5, x5, 10101)
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// ORI:
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m4_asm(ORI, x6, x1, 1011100)
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m4_asm(XORI, x6, x6, 1011100)
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// ADDI:
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m4_asm(ADDI, x7, x1, 111)
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m4_asm(XORI, x7, x7, 11101)
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// ADDI:
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m4_asm(SLLI, x8, x1, 110)
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m4_asm(XORI, x8, x8, 10101000001)
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// SLLI:
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m4_asm(SRLI, x9, x1, 10)
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m4_asm(XORI, x9, x9, 100)
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// AND:
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m4_asm(AND, r10, x1, x2)
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m4_asm(XORI, x10, x10, 100)
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// OR:
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m4_asm(OR, x11, x1, x2)
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m4_asm(XORI, x11, x11, 10110)
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// XOR:
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m4_asm(XOR, x12, x1, x2)
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m4_asm(XORI, x12, x12, 10011)
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// ADD:
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m4_asm(ADD, x13, x1, x2)
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m4_asm(XORI, x13, x13, 11101)
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// SUB:
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m4_asm(SUB, x14, x1, x2)
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m4_asm(XORI, x14, x14, 1111)
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// SLL:
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m4_asm(SLL, x15, x2, x2)
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m4_asm(XORI, x15, x15, 1110000001)
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// SRL:
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m4_asm(SRL, x16, x1, x2)
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m4_asm(XORI, x16, x16, 1)
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// SLTU:
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m4_asm(SLTU, x17, x2, x1)
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m4_asm(XORI, x17, x17, 0)
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// SLTIU:
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m4_asm(SLTIU, x18, x2, 10101)
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m4_asm(XORI, x18, x18, 0)
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// LUI:
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m4_asm(LUI, x19, 0)
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m4_asm(XORI, x19, x19, 1)
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// SRAI:
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m4_asm(SRAI, x20, x3, 1)
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m4_asm(XORI, x20, x20, 111111111111)
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// SLT:
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m4_asm(SLT, x21, x3, x1)
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m4_asm(XORI, x21, x21, 0)
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// SLTI:
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m4_asm(SLTI, x22, x3, 1)
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m4_asm(XORI, x22, x22, 0)
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// SRA:
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m4_asm(SRA, x23, x1, x2)
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m4_asm(XORI, x23, x23, 1)
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// AUIPC:
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m4_asm(AUIPC, x4, 100)
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m4_asm(SRLI, x24, x4, 111)
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m4_asm(XORI, x24, x24, 10000000)
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// JAL:
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m4_asm(JAL, x25, 10) // x25 = PC of next instr
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m4_asm(AUIPC, x4, 0) // x4 = PC
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m4_asm(XOR, x25, x25, x4) # AUIPC and JAR results are the same.
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m4_asm(XORI, x25, x25, 1)
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// JALR:
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m4_asm(JALR, x26, x4, 10000)
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m4_asm(SUB, x26, x26, x4) // JALR PC+4 - AUIPC PC
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m4_asm(ADDI, x26, x26, 111111110001) // - 4 instrs, + 1
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// SW & LW:
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m4_asm(SW, x2, x1, 1)
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m4_asm(LW, x27, x2, 1)
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m4_asm(XORI, x27, x27, 10100)
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// Write 1 to remaining registers prior to x30 just to avoid concern.
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m4_asm(ADDI, x28, x0, 1)
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m4_asm(ADDI, x29, x0, 1)
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// Terminate with success condition (regardless of correctness of register values):
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m4_asm(ADDI, x30, x0, 1)
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m4_asm(JAL, x0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
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'])m4_ifelse(['$1'], [''], ['m4_asm_end()'], ['m4_asm_end_tlv()'])'])
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m4_define_vector(['M4_WORD'], 32)
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m4_define_vector(['M4_WORD'], 32)
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m4_define(['M4_EXT_I'], 1)
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m4_define(['M4_EXT_I'], 1)
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@ -13,14 +107,14 @@ m4+definitions(['
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m4_echo(m4tlv_riscv_gen__body())
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m4_echo(m4tlv_riscv_gen__body())
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m4_define(['M4_MAX_CYC'], 70) // Default for m4+test_prog().
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// A single-line M4 macro instantiated at the end of the asm code.
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// A single-line M4 macro instantiated at the end of the asm code.
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// It actually produces a definition of an SV macro that instantiates the IMem conaining the program (that can be parsed without \SV_plus).
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// It actually produces a definition of an SV macro that instantiates the IMem conaining the program (that can be parsed without \SV_plus).
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m4_define(['m4_asm_end'], ['`define READONLY_MEM(ADDR, DATA) logic [31:0] instrs [0:M4_NUM_INSTRS-1]; assign DATA = instrs[ADDR[$clog2($size(instrs)) + 1 : 2]]; assign instrs = '{m4_instr0['']m4_forloop(['m4_instr_ind'], 1, M4_NUM_INSTRS, [', m4_echo(['m4_instr']m4_instr_ind)'])};'])
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m4_define(['m4_asm_end'], ['`define READONLY_MEM(ADDR, DATA) logic [31:0] instrs [0:M4_NUM_INSTRS-1]; assign DATA = instrs[ADDR[$clog2($size(instrs)) + 1 : 2]]; assign instrs = '{m4_instr0['']m4_forloop(['m4_instr_ind'], 1, M4_NUM_INSTRS, [', m4_echo(['m4_instr']m4_instr_ind)'])};'])
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m4_define(['m4_asm_end_tlv'], ['`define READONLY_MEM(ADDR, DATA) logic [31:0] instrs [0:M4_NUM_INSTRS-1]; assign DATA \= instrs[ADDR[\$clog2(\$size(instrs)) + 1 : 2]]; assign instrs \= '{m4_instr0['']m4_forloop(['m4_instr_ind'], 1, M4_NUM_INSTRS, [', m4_echo(['m4_instr']m4_instr_ind)'])};'])
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m4_define(['m4_asm_end_tlv'], ['`define READONLY_MEM(ADDR, DATA) logic [31:0] instrs [0:M4_NUM_INSTRS-1]; assign DATA \= instrs[ADDR[\$clog2(\$size(instrs)) + 1 : 2]]; assign instrs \= '{m4_instr0['']m4_forloop(['m4_instr_ind'], 1, M4_NUM_INSTRS, [', m4_echo(['m4_instr']m4_instr_ind)'])};'])
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'])
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'])
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\TLV test_prog()
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m4_test_prog()
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// Register File
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// Register File
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\TLV rf(_entries, _width, $_reset, $_port1_en, $_port1_index, $_port1_data, $_port2_en, $_port2_index, $_port2_data, $_port3_en, $_port3_index, $_port3_data)
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\TLV rf(_entries, _width, $_reset, $_port1_en, $_port1_index, $_port1_data, $_port2_en, $_port2_index, $_port2_data, $_port3_en, $_port3_index, $_port3_data)
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@ -633,97 +727,6 @@ m4+definitions(['
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(! $reset && $next_pc[31:0] == $pc[31:0]);
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(! $reset && $next_pc[31:0] == $pc[31:0]);
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*passed = >>2$passed_cond;
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*passed = >>2$passed_cond;
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\TLV test_prog()
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// /=======================\
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// | Test each instruction |
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// \=======================/
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//
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// Some constant values to use as operands.
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m4_asm(ADDI, x1, x0, 10101) // An operand value of 21.
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m4_asm(ADDI, x2, x0, 111) // An operand value of 7.
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m4_asm(ADDI, x3, x0, 111111111100) // An operand value of -4.
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// Execute one of each instruction, XORing subtracting (via ADDI) the expected value.
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// ANDI:
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m4_asm(ANDI, x5, x1, 1011100)
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m4_asm(XORI, x5, x5, 10101)
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// ORI:
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m4_asm(ORI, x6, x1, 1011100)
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m4_asm(XORI, x6, x6, 1011100)
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// ADDI:
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m4_asm(ADDI, x7, x1, 111)
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m4_asm(XORI, x7, x7, 11101)
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// ADDI:
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m4_asm(SLLI, x8, x1, 110)
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m4_asm(XORI, x8, x8, 10101000001)
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// SLLI:
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m4_asm(SRLI, x9, x1, 10)
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m4_asm(XORI, x9, x9, 100)
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// AND:
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m4_asm(AND, r10, x1, x2)
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m4_asm(XORI, x10, x10, 100)
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// OR:
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m4_asm(OR, x11, x1, x2)
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m4_asm(XORI, x11, x11, 10110)
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// XOR:
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m4_asm(XOR, x12, x1, x2)
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m4_asm(XORI, x12, x12, 10011)
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// ADD:
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m4_asm(ADD, x13, x1, x2)
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m4_asm(XORI, x13, x13, 11101)
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// SUB:
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m4_asm(SUB, x14, x1, x2)
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m4_asm(XORI, x14, x14, 1111)
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// SLL:
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m4_asm(SLL, x15, x2, x2)
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m4_asm(XORI, x15, x15, 1110000001)
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// SRL:
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m4_asm(SRL, x16, x1, x2)
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m4_asm(XORI, x16, x16, 1)
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// SLTU:
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m4_asm(SLTU, x17, x2, x1)
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m4_asm(XORI, x17, x17, 0)
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// SLTIU:
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m4_asm(SLTIU, x18, x2, 10101)
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m4_asm(XORI, x18, x18, 0)
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// LUI:
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m4_asm(LUI, x19, 0)
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m4_asm(XORI, x19, x19, 1)
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// SRAI:
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m4_asm(SRAI, x20, x3, 1)
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m4_asm(XORI, x20, x20, 111111111111)
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// SLT:
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m4_asm(SLT, x21, x3, x1)
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m4_asm(XORI, x21, x21, 0)
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// SLTI:
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m4_asm(SLTI, x22, x3, 1)
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m4_asm(XORI, x22, x22, 0)
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// SRA:
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m4_asm(SRA, x23, x1, x2)
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m4_asm(XORI, x23, x23, 1)
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// AUIPC:
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m4_asm(AUIPC, x4, 100)
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m4_asm(SRLI, x24, x4, 111)
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m4_asm(XORI, x24, x24, 10000000)
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// JAL:
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m4_asm(JAL, x25, 10) // x25 = PC of next instr
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m4_asm(AUIPC, x4, 0) // x4 = PC
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m4_asm(XOR, x25, x25, x4) # AUIPC and JAR results are the same.
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m4_asm(XORI, x25, x25, 1)
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// JALR:
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m4_asm(JALR, x26, x4, 10000)
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m4_asm(SUB, x26, x26, x4) // JALR PC+4 - AUIPC PC
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m4_asm(ADDI, x26, x26, 111111110001) // - 4 instrs, + 1
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// SW & LW:
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m4_asm(SW, x2, x1, 1)
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m4_asm(LW, x27, x2, 1)
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m4_asm(XORI, x27, x27, 10100)
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// Write 1 to remaining registers prior to x30 just to avoid concern.
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m4_asm(ADDI, x28, x0, 1)
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m4_asm(ADDI, x29, x0, 1)
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// Terminate with success condition (regardless of correctness of register values):
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m4_asm(ADDI, x30, x0, 1)
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m4_asm(JAL, x0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
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m4_asm_end_tlv()
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// (A copy of this appears in the shell code.)
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// (A copy of this appears in the shell code.)
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\TLV sum_prog()
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\TLV sum_prog()
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