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# Gates-To-RISC-V-Course
# Building a RISC-V CPU Core
Accompanying resources for the [Building a RISC-V CPU Core](https://courses.edx.org/TBD) [EdX])(https://edx.org/) course by [Steve Hoover](https://www.linkedin.com/in/steve-hoover-a44b607/) of [Redwood EDA](https://redwoodeda.com), [Linux Foundation](https://www.linuxfoundation.org/), and [RISC-V International](https://riscv.org).
## RISC-V Starting-Point Code
To begin the first RISC-V lab, use this link to <a href="https://makerchip.com/sandbox?code_url=https:%2F%2Fraw.githubusercontent.com%2Fstevehoover%2FLF-Building-a-RISC-V-CPU-Core%2Fmaster%2Friscv_shell.tlv" target="_blank" atom_fix="_">open starting-point code in makerchip</a>.
## RISC-V Reference Solution
In case you get stuck, use this <a href="https://makerchip.com/sandbox?code_url=https:%2F%2Fraw.githubusercontent.com%2Fstevehoover%2FLF-Building-a-RISC-V-CPU-Core%2Fmaster%2Friscv_solutions.tlv" target="_blank" atom_fix="_">reference solution</a> to help with syntax, etc.
## Final Result:
Final Result:
![Final Core](lib/riscv.svg)