vtimofei
/
LF-Building-a-RISC-V-CPU-Core
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Update README.md

This commit is contained in:
Steve Hoover 2021-02-08 13:50:44 -05:00 committed by GitHub
parent f206e7a370
commit 5165d3a3b8
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 13 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
README.md
View File

@ -1,4 +1,15 @@
# Gates-To-RISC-V-Course # Building a RISC-V CPU Core
Accompanying resources for the [Building a RISC-V CPU Core](https://courses.edx.org/TBD) [EdX])(https://edx.org/) course by [Steve Hoover](https://www.linkedin.com/in/steve-hoover-a44b607/) of [Redwood EDA](https://redwoodeda.com), [Linux Foundation](https://www.linuxfoundation.org/), and [RISC-V International](https://riscv.org).
## RISC-V Starting-Point Code
To begin the first RISC-V lab, use this link to <a href="https://makerchip.com/sandbox?code_url=https:%2F%2Fraw.githubusercontent.com%2Fstevehoover%2FLF-Building-a-RISC-V-CPU-Core%2Fmaster%2Friscv_shell.tlv" target="_blank" atom_fix="_">open starting-point code in makerchip</a>.
## RISC-V Reference Solution
In case you get stuck, use this <a href="https://makerchip.com/sandbox?code_url=https:%2F%2Fraw.githubusercontent.com%2Fstevehoover%2FLF-Building-a-RISC-V-CPU-Core%2Fmaster%2Friscv_solutions.tlv" target="_blank" atom_fix="_">reference solution</a> to help with syntax, etc.
## Final Result:
Final Result:
![Final Core](lib/riscv.svg) ![Final Core](lib/riscv.svg)