diff --git a/lib/risc-v_shell_lib.tlv b/lib/risc-v_shell_lib.tlv
index a41d84b..2a0046a 100644
--- a/lib/risc-v_shell_lib.tlv
+++ b/lib/risc-v_shell_lib.tlv
@@ -114,7 +114,7 @@ m4+definitions(['
 '])
 
 \TLV test_prog()
-   m4_test_prog()
+   m4_test_prog(['TLV'])
 
 // Register File
 \TLV rf(_entries, _width, $_reset, $_port1_en, $_port1_index, $_port1_data, $_port2_en, $_port2_index, $_port2_data, $_port3_en, $_port3_index, $_port3_data)
diff --git a/risc-v_shell.tlv b/risc-v_shell.tlv
index d9ddbcc..722406f 100644
--- a/risc-v_shell.tlv
+++ b/risc-v_shell.tlv
@@ -6,7 +6,7 @@
    m4_include_lib(['https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/main/lib/risc-v_shell_lib.tlv'])
 
 
-                   
+
    //---------------------------------------------------------------------------------
    // /====================\
    // | Sum 1 to 9 Program |
@@ -34,10 +34,11 @@
    m4_define(['M4_MAX_CYC'], 50)
    //---------------------------------------------------------------------------------
 
-                   
+
 
 \SV
    m4_makerchip_module   // (Expanded in Nav-TLV pane.)
+   
 \TLV
    
    $reset = *reset;
diff --git a/risc-v_solutions.tlv b/risc-v_solutions.tlv
index a530e1e..540e253 100644
--- a/risc-v_solutions.tlv
+++ b/risc-v_solutions.tlv
@@ -18,7 +18,7 @@
    // ----------------------------------
    
    // Include solutions.
-   m4_include_makerchip_hidden(['LF_workshop_solutions.private.tlv'])       
+   m4_include_makerchip_hidden(['LF_workshop_solutions.private.tlv'])
 
 \SV
    // Macro providing required top-level module definition, random